S9S12G64F0MLH Freescale Semiconductor, S9S12G64F0MLH Datasheet - Page 339
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S9S12G64F0MLH
Manufacturer Part Number
S9S12G64F0MLH
Description
16-bit Microcontrollers - MCU S12 Core,64k Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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MARK1
MARK2
SUB_1
ADDR1
IRQ_ISR LDAB
MARK1
IRQ_ISR LDAB
SUB_1
ADDR1
8.4.5.2.2
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the
DBG module writes this value into a background register. This prevents consecutive duplicate address
entries in the Trace Buffer resulting from repeated branches.
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG
module is designed to help find.
8.4.5.2.3
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This
mode is intended to supply additional information on indexed, indirect addressing modes where storing
only the destination address would not provide all information required for a user to determine where the
code is in error. This mode also features information bit storage to the trace buffer, for each address byte
Freescale Semiconductor
LDX
JMP
NOP
BRN
NOP
DBNE
STAB
RTI
LDX
JMP
STAB
RTI
BRN
NOP
DBNE
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
The execution flow taking into account the IRQ is as follows
Loop1 Mode
Detail Mode
#SUB_1
0,X
*
A,PART5
#$F0
VAR_C1
#SUB_1
0,X
#$F0
VAR_C1
*
A,PART5
MC9S12G Family Reference Manual, Rev.1.23
; IRQ interrupt occurs during execution of this
;
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
;
;
;
;
;
;
S12S Debug Module (S12SDBGV2)
341
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