S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 145
S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
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DDRH
DDRH
DDRH
DDRH
DDRH
DDRH
Field
7
6
5
4
3
2
Port H data direction—
This register controls the data direction of pin 7.
The enabled SCI5 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 6.
The enabled SCI5 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 5.
The enabled SCI4 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 4.
The enabled SCI4 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 3.
The enabled SCI7 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 2.
The enabled SCI7 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Table 2-51. DDRH Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
145
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