S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 193

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

3.3.2
3.3.2.1
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
The MMCCTL0 register is used to control external bus functions, like:
Freescale Semiconductor
Address: 0x000A PRR
1. ROMON is bit[0] of the register MMCTL1 (see
Reset
•
•
1. Disabled: feature always inactive.
2. Enabled: activity is controlled by the appropriate register bit value.
W
R
Availability of chip selects. (See
Control of different external stretch mechanism. For more detail refer to the S12X_EBI
BlockGuide.
CS0E[1:0], CS1E[1:0],
CS2E[1:0], CS3E[1:0]
CS3E1
Register Descriptions
MMC Control Register (MMCCTL0)
Register Bit
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
= Unimplemented or Reserved
CS3E0
0
6
Figure 3-3. MMC Control Register (MMCCTL0)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 3-5. Chip Selects Function Activity
Disabled
CS2E1
NS
0
5
Table 3-5
Figure
(1)
Disabled
3-10)
CAUTION
CS2E0
SS
0
4
and
Table
Enabled
CS1E1
NX
3-6)
Chip Modes
0
3
(2)
Chapter 3 Memory Mapping Control (S12XMMCV4)
Disabled
ES
CS1E0
0
2
Enabled
EX
CS0E1
0
1
Disabled
ST
ROMON
CS0E0
0
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1