S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 83

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Vector Address
Freescale Semiconductor
Vector base + $8A
Vector base + $7E
Vector base + $7C
Vector base + $7A
Vector base + $6E
Vector base + $6C
Vector base + $6A
Vector base + $5E
Vector base + $5C
Vector base + $5A
Vector base + $88
Vector base + $86
Vector base + $84
Vector base + $82
Vector base + $80
Vector base + $78
Vector base + $76
Vector base + $74
Vector base + $72
Vector base + $70
Vector base + $68
Vector base + $66
Vector base + $64
Vector base + $62
Vector base + $60
Vector base + $58
Vector base + $56
Vector base + $54
Vector base + $52
Vector base + $50
(1)
Channel
XGATE
ID
$3D
$3C
$3B
$3A
$2E
$2D
$2C
$2B
$2A
$45
$44
$43
$42
$41
$40
$3F
$39
$38
$37
$36
$35
$34
$33
$32
$2F
$29
$28
—
(2)
Table 1-14. Interrupt Vector Locations (Sheet 3 of 4)
Autonomous periodical interrupt (API)
Periodic interrupt timer channel 0
Periodic interrupt timer channel 1
Periodic interrupt timer channel 2
Periodic interrupt timer channel 3
Periodic interrupt timer channel 4
Periodic interrupt timer channel 5
Periodic interrupt timer channel 6
Periodic interrupt timer channel 7
MC9S12XE-Family Reference Manual Rev. 1.25
High Temperature Interrupt
Low-voltage interrupt (LVI)
XGATE software trigger 0
XGATE software trigger 1
XGATE software trigger 2
XGATE software trigger 3
XGATE software trigger 4
XGATE software trigger 5
XGATE software trigger 6
XGATE software trigger 7
TIM timer channel 0
TIM timer channel 1
TIM timer channel 2
Interrupt Source
IIC1 Bus
SCI2
SCI3
SCI4
SCI5
SCI7
Reserved
Reserved
Mask
CCR
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
VREGAPICTRL (APIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
Chapter 1 Device Overview MC9S12XE-Family
VREGHTCL (HTIE)
VREGCTRL (LVIE)
PITINTE (PINTE0)
PITINTE (PINTE1)
PITINTE (PINTE2)
PITINTE (PINTE3)
PITINTE (PINTE4)
PITINTE (PINTE5)
PITINTE (PINTE6)
PITINTE (PINTE7)
XGMCTL (XGIE)
XGMCTL (XGIE)
XGMCTL (XGIE)
XGMCTL (XGIE)
XGMCTL (XGIE)
XGMCTL (XGIE)
XGMCTL (XGIE)
XGMCTL (XGIE)
Local Enable
IBCR (IBIE)
SCI2CR2
SCI3CR2
SCI4CR2
SCI5CR2
SCI7CR2
TIE (C0I)
TIE (C1I)
TIE (C2I)
Wake up
STOP
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Wake up
WAIT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
83