S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 631

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Figure 16-24
identifiers. The mapping of standard identifiers into the IDR registers is shown in
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
1. Exception: The transmit buffer priority registers are 0 out of reset.
Freescale Semiconductor
1. Not applicable for receive buffers
Address
0x00XA
0x00XB
0x00XC
0x00XD
0x00XE
0x00X0
0x00X1
0x00X2
0x00X3
0x00X4
0x00X5
0x00X6
0x00X7
0x00X8
0x00X9
0x00XF
Offset
shows the common 13-byte data structure of receive and transmit buffers for extended
IDR0 — Identifier Register 0
IDR1 — Identifier Register 1
IDR2 — Identifier Register 2
IDR3 — Identifier Register 3
DSR0 — Data Segment Register 0
DSR1 — Data Segment Register 1
DSR2 — Data Segment Register 2
DSR3 — Data Segment Register 3
DSR4 — Data Segment Register 4
DSR5 — Data Segment Register 5
DSR6 — Data Segment Register 6
DSR7 — Data Segment Register 7
DLR — Data Length Register
TBPR — Transmit Buffer Priority Register
TSRH — Time Stamp Register (High Byte)
TSRL — Time Stamp Register (Low Byte)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 16-26. Message Buffer Organization
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Register
(1)
Figure
Access
16-25.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
1
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