LPC11U24FBD48/301, NXP Semiconductors, LPC11U24FBD48/301, Datasheet - Page 19

• Manufacturer Part Number: LPC11U24FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB with USB
• Manufacturer: NXP Semiconductors

Specifications of LPC11U24FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11U2x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 6 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Data Rom Size: 2 KB
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11U2X
Product data sheet
7.10.1 Features
7.11.1 Features
7.12 I
7.11 SSP serial I/O controller
The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. Only a single master and a single slave can
communicate on the bus during a given data transfer. The SSP supports full duplex
transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and
from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
The LPC11U2x contain one I
The I
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
more than one bus master connected to the interface can be controlled the bus.
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C-bus serial I/O controller
Maximum USART data bit rate of 3.125 Mbit/s.
16 byte receive and transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
Support for RS-485/9-bit mode.
Support for modem control.
Support for synchronous mode.
Includes smart card interface.
Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments
SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
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C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 13 January 2012
2
C-bus controller.
32-bit ARM Cortex-M0 microcontroller
2
C-bus is a multi-master bus, and
LPC11U2x
© NXP B.V. 2012. All rights reserved.
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