MPC8536EBVTATLA Freescale Semiconductor, MPC8536EBVTATLA Datasheet - Page 104

• Manufacturer Part Number: MPC8536EBVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536EBVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

L
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in
3. A T
4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to
5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)
6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps
7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
Electrical Characteristics
2.22
The RX eye diagram in
any real PCI Express RX component.
Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement load (see
be larger than the minimum Receiver eye diagram measured over a range of systems at the input Receiver of any real PCI
Express component. The degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon
parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test
measurement load. The input Receiver eye diagram is implementation specific and is not specified. RX component designer
should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in
Figure
measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate
the center of the eye diagram.
The eye diagram must be valid for any 250 consecutive UIs.
104
TX-SKEW
as the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in
clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must
be used as a reference for the eye diagram.
interconnect collected any 250 consecutive UIs. The T
which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any
250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point
in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must
be used as the reference for the eye diagram.
300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50 ohms to ground for both the D+ and D- line (that is, as measured
by a Vector Network Analyzer with 50 ohm probes - see
return loss measurement.
there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.
ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated
data.
RX-EYE
Symbol
70) expected at the input Receiver based on some adequate combination of system simulations and the Return Loss
= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
Receiver Compliance Eye Diagrams
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Table 72. Differential Receiver (RX) Input Specifications (continued)
Total Skew
Figure 70
Parameter
is specified using the passive compliance/test measurement load (see
Min
—
Nom
—
RX-EYE-MEDIAN-to-MAX-JITTER
Figure
Max
20
71). Note: that the series capacitors CTX is optional for the
Units
ns
Skew across all lanes on a Link. This includes
variation in the length of SKP ordered set (for
example, COM and one to five Symbols) at
the RX as well as any delay differences
arising from the interconnect itself.
specification ensures a jitter distribution in
Comments
Figure 71
Freescale Semiconductor
Figure
Figure
should be used
Figure
71) in place of
70). If the
71) will