MPC8536EBVTATLA Freescale Semiconductor, MPC8536EBVTATLA Datasheet - Page 46

• Manufacturer Part Number: MPC8536EBVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536EBVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

At recommended operating conditions with L/TV
Electrical Characteristics
This figure shows the MII transmit AC timing diagram.
2.9.2.3.2
This table provides the MII receive AC timing specifications.
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
This figure provides the AC test load for eTSEC.
46
for inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,
the subscript of t
appropriate letter: R (rise) or F (fall).
(first two letters of functional block)(reference)(state)(signal)(state)
MII Receive AC Timing Specifications
Parameter/Condition
MRX
TXD[3:0]
TX_CLK
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
TX_EN
TX_ER
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
Output
Table 31. MII Receive AC Timing Specifications
MRX
Figure 19. MII Transmit AC Timing Diagram
t
MTXH
clock reference (K) going to the low (L) state or hold time. Note that, in general, the
MRDXKL
DD
Figure 20. eTSEC AC Test Load
of 3.3 V ± 5%.
t
MTX
Z
0
symbolizes MII receive timing (GR) with respect to the time data input signals
= 50 Ω
t
t
MTKHDX
Symbol
MRXH
t
t
t
MTXF
MRDVKH
MRDXKH
t
t
t
t
MRXR
MRXF
MRX
MRX
/t
for outputs. For example, t
MRX
(first two letters of functional block)(signal)(state) (reference)(state)
1
R
t
L
MTXR
= 50 Ω
10.0
10.0
Min
1.0
1.0
—
—
35
LV
DD
Typ
400
MRDVKH
40
—
—
—
—
—
/2
MRX
Freescale Semiconductor
clock reference (K) going
symbolizes MII receive
Max
4.0
4.0
65
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
%