MPC8536EBVTATLA Freescale Semiconductor, MPC8536EBVTATLA Datasheet - Page 29

• Manufacturer Part Number: MPC8536EBVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536EBVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

2.4.4
This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the chip.
2.4.5
This table provides the DDR clock (DDRCLK) AC timing specifications for the chip.
Freescale Semiconductor
At recommended operating conditions with
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK rise and fall time
LV
LV
EC_GTX_CLK125 duty cycle
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TVDD=2.5V, and from 0.6 and 2.7V for
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125
DD,
DD,
L/TVDD=3.3V at 0.6 V and 2.7 V.
duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See
reference clock.
DDRCLK frequency
DDRCLK cycle time
DDRCLK rise and fall time
DDRCLK duty cycle
DDRCLK jitter
Notes:
1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex
2. Rise and fall times for DDRCLK are measured at 0.6 V and 2.7 V.
3. The DDRCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
4. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and
clock frequency does not exceed the maximum or minimum operating frequencies. See
“DDR/DDRCLK PLL
allow cascade-connected PLL-based devices to track DDRCLK drivers with the specified jitter.
60 kHz on DDRCLK.
TV
TV
DD =
DD =
Parameter/Condition
eTSEC Gigabit Reference Clock Timing
DDR Clock Timing
2.5V
3.3V
Parameter/Condition
1000Base-T for RGMII, RTBI
Section 2.9.2.6, “RGMII and RTBI AC Timing
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Ratio,” for ratio settings.
Table 8. EC_GTX_CLK125 AC Timing Specifications
GMII, TBI
Table 9. DDRCLK AC Timing Specifications
OV
DD
t
t
G125R
of 3.3V ± 5%.
G125H
Symbol
t
KHK
f
t
G125
G125
Symbol
f
t
t
/t
DDRCLK
DDRCLK
KH
/t
/t
G125F
G125
—
DDRCLK
, t
KL
Specifications,” for duty cycle for 10Base-T and 100Base-T
Min
45
47
—
—
—
Min
6.0
0.6
66
40
—
Typical
Typical
125
—
—
8
1.0
—
—
—
—
+/– 150
15.15
Max
Max
0.75
166
1.0
1.2
55
53
60
—
—
Section 2.23.4,
Electrical Characteristics
MHz
Unit
ns
ns
ps
MHz
%
Unit
ns
ns
%
Notes
3, 4
—
—
1
2
Notes
—
—
1
2
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