MPC8536EBVTATLA Freescale Semiconductor, MPC8536EBVTATLA Datasheet - Page 115

• Manufacturer Part Number: MPC8536EBVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536EBVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to
minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V
BV
have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected
to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values types
and quantity of bulk capacitors.
3.5
he SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SnV
transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to
power and ground should be done with multiple vias to further reduce inductance.
3.6
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active
low inputs should be tied to V
connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all
external V
3.7
The chip requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins including I
interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion will give unpredictable results.
The following pins must NOT be pulled down during power-on reset: TSEC1_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The UART_SOUT[0:1] and TEST_SEL pins must be set to a
proper state during POR configuration. Please refer to the pinlist table (see
See the PCI 2.2 specification for all pull-ups required for PCI.
3.8
The chip drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended
driver type (open drain for I
Freescale Semiconductor
DD
•
•
•
, OV
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls
of the chip. Where the board has blind vias, these capacitors should be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
chip as close to the supply and ground connections as possible.
Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SnV
ground plane on each side of the chip. This should be done for all SerDes supplies.
Third, between the chip and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance
(ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all
SerDes supplies.
DD,
DD
SerDes Block Power Supply Decoupling Recommendations
Connection Recommendations
Pull-Up and Pull-Down Resistor Requirements
Output Buffer DC Impedance
TV
, GV
DD
DD
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
, BV
, and LV
DD
, OV
2
C).
DD
DD,
DD
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
TV
, GV
DD
, BV
DD
, and LV
DD
, OV
DD
DD
, GV
and GND pins of the chip.
DD
, and LV
DD
as required. All unused active high inputs should be
Table
62) of the individual chip for more details.
DD
and XnV
Hardware Design Considerations
DD
and XnV
DD
) to ensure low jitter on
2
C pins and MPIC
DD
) to the board
DD
Figure
, TV
DD
78.
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