MPC8536EBVTATLA Freescale Semiconductor, MPC8536EBVTATLA Datasheet - Page 113

• Manufacturer Part Number: MPC8536EBVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536EBVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

The heat sink removes most of the heat from the chip for most applications. Heat generated on the active side of the chip is
conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat
sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance
are the dominant terms.
2.24.3.2
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The
performance of thermal interface materials improves with increased contact pressure. This performance characteristic chart is
generally provided by the thermal interface vendors.
3
This section provides electrical and thermal design recommendations for successful application of the chip.
3.1
This chip includes seven PLLs:
3.2
3.2.1
Each of the PLLs listed above is provided with power through independent power supply pins (AV
AV
preferably these voltages will be derived directly from V
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent
filter circuits per PLL power supply as illustrated in
to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built
with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.
Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors
of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
nearby circuits. It should be possible to route directly from the capacitors to the AV
FC-PBGA the footprint, without the inductance of vias.
Freescale Semiconductor
DD
•
•
•
•
•
•
•
_PCI, AV
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
Section 2.23.2, “CCB/SYSCLK PLL Ratio.”
The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500
core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in
“e500 Core PLL
The PCI PLL generates the clocking for the PCI bus
The local bus PLL generates the clock for the local bus.
There is a PLL for the SerDes1 block to be used for PCI Express interface
There is a PLL for the SerDes2 block to be used for SGMII and SATA interfaces.
The DDR PLL generates the DDR clock from the externally supplied DDRCLK input in asynchronous mode. The
frequency ratio between the DDR clock and DDRCLK is described in
Hardware Design Considerations
System Clocking
Power Supply Design and Sequencing
PLL Power Supply Filtering
DD
Thermal Interface Materials
_LBIU, and AV
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Ratio.”
DD
_SRDS respectively). The AV
Figure
DD
75, one to each of the AV
through a low frequency filter scheme such as the following.
DD
DD
level should always be equivalent to V
pin being supplied to minimize noise coupled from
Section 2.23.4, “DDR/DDRCLK PLL Ratio.”
DD
DD
pin, which is on the periphery of 783
pins. By providing independent filters
Hardware Design Considerations
DD
_PLAT, AV
DD
Section 2.23.3,
, and
DD
_CORE,
113