DAC1008D750HN/C1 NXP Semiconductors, DAC1008D750HN/C1 Datasheet - Page 12

• Manufacturer Part Number: DAC1008D750HN/C1
• Description: Digital to Analog Converters - DAC DL 10BIT DAC 750MSPS 2X 4X OR 8X INT
• Manufacturer: NXP Semiconductors

Specifications of DAC1008D750HN/C1

• Rohs: yes
• Factory Pack Quantity: 260

NXP Semiconductors
10. Application information
DAC1008D750
Product data sheet
10.1 General description
The DAC1008D750 is a dual 10-bit DAC operating up to 750 Msps. With a maximum input
data rate of up to 312.5 Msps and a maximum output sampling rate of 750 Msps, the
DAC1008D750 allows more flexibility for wide bandwidth and multi-carrier systems.
Combined with its quadrature modulator and 32-bit NCO, the DAC1008D750 simplifies
the frequency selection of the system. This is also possible because of the 2, 4 or 8
interpolation filters which remove undesired images.
DAC1008D750 supports the following JESD204A key features:
DAC1008D750 can be interfaced with any logic device that features high-speed SERDES
functionality. This macro is now widely available in FPGA from different vendors.
Standalone SERDES ICs can also be used.
To enhance the intrinsic board layout simplification of the JESD204A standard, NXP
includes polarity swapping for each of the lanes and additionally offers lane swapping.
Each physical lane can be configured logically as lane0, lane1, lane2 or lane3.
This device is MCDA-ML compliant, offering inter-lane alignment between several
devices. Samples alignment between devices is maintained up to output level because of
an NXP proprietary mechanism. One device is configured as the master and all the others
are configured as slaves. These will automatically align their output samples to the master
ones. Therefore, a system with several DAC1008D750s can produce data with a
guaranteed alignment of less than 1 DAC output clock period.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN. This provides a full-scale output current of up to 20 mA. An internal
reference is available for the reference current which is externally adjustable using pin
VIRES.
The DAC1008D750 must be configured before operating. Therefore, it features an SPI
slave interface to access internal registers. Some of these registers also provide
information about the JESD204A interface status.
The DAC1008D750 requires supplies of both 3.3 V and 1.8 V. The 1.8 V supply has
separate digital and analog power supply pins. The clock input is LVDS compliant.
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10-bit/8-bit decoding
Code group synchronization
inter-lane alignment
1 + x
Character replacement
TX/RX synchronization management via SYNC signals
Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device
14
+ x
15
All information provided in this document is subject to legal disclaimers.
scrambling polynomial
Rev. 3 — 31 January 2012
2, 4 or 8 interpolating DAC with JESD204A
DAC1008D750
© NXP B.V. 2012. All rights reserved.
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