DAC1008D750HN/C1 NXP Semiconductors, DAC1008D750HN/C1 Datasheet - Page 96

• Manufacturer Part Number: DAC1008D750HN/C1
• Description: Digital to Analog Converters - DAC DL 10BIT DAC 750MSPS 2X 4X OR 8X INT
• Manufacturer: NXP Semiconductors

Specifications of DAC1008D750HN/C1

• Rohs: yes
• Factory Pack Quantity: 260

NXP Semiconductors
Table 60. MAINCONTROL register (address 00h) bit
Table 61. JCLK_CNTRL register (address 03h) bit
Table 62. RST_EXT_FCLK register (address 04h) bit
Table 63. RST_EXT_DCLK register (address 05h) bit
Table 64. DCSMU_PREDIVCNT register (address 06h)
Table 65. PLL_CHARGETIME register (address 07h)
Table 66. PLL_RUN_IN_TIME register (address 08h)
Table 67. CA_RUN_IN_TIME register (address 09h)
Table 68. SET_VCM_VOLTAGE register (address 16h)
Table 69. SET_SYNC register (address 17h) bit
Table 70. TYPE_ID register (address 1Bh) bit
Table 71. DAC_VERSION register (address 1Ch) bit
Table 72. DIG_VERSION register (address 1Dh) bit
Table 73. JRX_ANA_VERSION register (address 1Eh)
Table 74. PAGE_ADDRESS register (address 1Fh) bit
Table 75. Lane common-mode voltage adjustment . . . . .56
Table 76. SYNC common-mode voltage adjustment . . . .56
Table 77. SYNC swing voltage adjustment . . . . . . . . . . .56
Table 78. Page 4 register allocation map . . . . . . . . . . . .57
Table 79. SR_DLP_0 register (address 00h) bit
Table 80. SR_DLP_1 register (address 01h) bit
Table 81. FORCE_LOCK register (address 02h) bit
Table 82. MAN_LOCK_LN_1_0 register (address 03h)
Table 83. MAN_LOCK_2_0 register (address 04h) bit
Table 84. CA_CNTRL register (address 05h) bit
Table 85. SCR_CNTRL register (address 06h) bit
Table 86. ILA_CNTRL register (address 07h) bit
Table 87. FORCE_ALIGN register (address 08h) bit
DAC1008D750
Product data sheet
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
bit description . . . . . . . . . . . . . . . . . . . . . . . . .60
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 31 January 2012
Table 88. MAN_ALIGN_LN_0_1 register (address 09h)
Table 89. MAN_ALIGN_LN_2_3 register (address 0Ah)
Table 90. FA_ERR_HANDLING register (address 0Bh)
Table 91. SYNCOUT_MODE register (address 0Ch) bit
Table 92. LANE_POLARITY register (address 0Dh) bit
Table 93. LANE_SELECT register (address 0Eh) bit
Table 94. SOFT_RESET_SCRAMBLER register
Table 95. INIT_SCR_S15T8_LN0 register
Table 96. INIT_SCR_S7T1_LN0 (address 12h) bit
Table 97. INIT_SCR_S15T8_LN1 register
Table 98. INIT_SCR_S7T1_LN1 register
Table 99. INIT_SCR_S15T8_LN2 register
Table 100. INIT_SCR_S7T1_LN2 register
Table 101. INIT_SCR_S15T8_LN3 register
Table 102. INIT_SCR_S7T1_LN3 register
Table 103. INIT_ILA_BUFPTR_LN01 register
Table 104. INIT_ILA_BUFPTR_LN23 register
Table 105. ERROR_HANDLING register
Table 106. REINIT_CNTRL register (address 1Ch) bit
Table 107. PAGE_ADDRESS register (address 1Fh)
Table 108. Page 5 register allocation map . . . . . . . . . . . . 69
Table 109. ILA_MON_1_0 register (address 00h) bit
Table 110. ILA_MON_3_2 register (address 01h) bit
Table 111. ILA_BUF_ERR register (address 02h) bit
Table 112. CA_MON register (address 03h) bit
Table 113. DEC_FLAGS register (address 04h) bit
2, 4 or 8 interpolating DAC with JESD204A
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
(address 10h) bit description . . . . . . . . . . . . . . 65
(address 11h) bit description . . . . . . . . . . . . . . 65
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
(address 13h) bit description . . . . . . . . . . . . . . 66
(address 14h) bit description . . . . . . . . . . . . . . 66
(address 15h) bit description . . . . . . . . . . . . . . 66
(address 16h) bit description . . . . . . . . . . . . . . 66
(address 17h) bit description . . . . . . . . . . . . . . 66
(address 18h) bit description . . . . . . . . . . . . . . 66
(address 19h) bit description . . . . . . . . . . . . . . 66
(address 1Ah) bit description . . . . . . . . . . . . . 66
(address 1Bh) bit description . . . . . . . . . . . . . 67
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 68
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DAC1008D750
© NXP B.V. 2012. All rights reserved.
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