DAC1008D750HN/C1 NXP Semiconductors, DAC1008D750HN/C1 Datasheet - Page 95

DAC1008D750HN/C1

Manufacturer Part Number

DAC1008D750HN/C1

Description

Digital to Analog Converters - DAC DL 10BIT DAC 750MSPS 2X 4X OR 8X INT

Manufacturer

NXP Semiconductors

Datasheet

1.DAC1008D750HNC1.pdf (99 pages)

Specifications of DAC1008D750HN/C1

Rohs

yes

Factory Pack Quantity

260

Current page: 95 of 99
Download datasheet (508Kb)

NXP Semiconductors

16. Tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10. Interpolation filter coefficients . . . . . . . . . . . . .27

Table 11. Inversion filter coefficients . . . . . . . . . . . . . . . .29

Table 12. DAC transfer function . . . . . . . . . . . . . . . . . . .29

Table 13. I

Table 14. I

Table 15. Digital offset adjustment . . . . . . . . . . . . . . . . .32

Table 16. Auxiliary DAC transfer function . . . . . . . . . . . .33

Table 17. Page 0 register allocation map . . . . . . . . . . . .39

Table 18. COMMON register (address 00h) bit

Table 19. TXCFG register (address 01h) bit description .41

Table 20. PLLCFG register (address 02h) bit description 42

Table 21. FREQNCO_LSB register (address 03h) bit

Table 22. FREQNCO_LISB register (address 04h) bit

Table 23. FREQNCO_UISB register (address 05h) bit

Table 24. FREQNCO_MSB register (address 06h) bit

Table 25. PHINCO_LSB register (address 07h) bit

Table 26. PHINCO_MSB register (address 08h) bit

Table 27. DAC_A_CFG_1 register (address 09h) bit

Table 28. DAC_A_CFG_2 register (address 0Ah) bit

Table 29. DAC_A_CFG_3 register (address 0Bh) bit

Table 30. DAC_B_CFG_1 register (address 0Ch) bit

Table 31. DAC_B_CFG_2 register (address 0Dh) bit

Table 32. DAC_B_CFG_3 register (address 0Eh) bit

Table 33. DAC_CFG register (address 0Fh) bit

Table 34. DAC_CURRENT_0 register (address 11h)

DAC1008D750

Product data sheet

Read or Write mode access description . . . . .24

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Ordering information . . . . . . . . . . . . . . . . . . . . .2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6

Thermal characteristics . . . . . . . . . . . . . . . . . . .6

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .7

Digital Layer Processing Latency . . . . . . . . . . .13

Number of bytes to be transferred . . . . . . . . . .24

SPI timing characteristics . . . . . . . . . . . . . . . .25

O(fs)

coarse adjustment . . . . . . . . . . . . . . . . . .31

fine adjustment . . . . . . . . . . . . . . . . . . . .31

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 31 January 2012

Table 35. DAC_CURRENT_1 register (address 12h)

Table 36. DAC_CURRENT_2 register (address 13h)

Table 37. DAC_CURRENT_3 register (address 14h)

Table 38. DAC_SEL_PH_FINE register (address 15h)

Table 39. PHASECORR_CNTRL0 register

Table 40. PHASECORR_CNTRL1 register

Table 41. DAC_A_AUX_MSB register (address 1Ah)

Table 42. DAC_A_AUX_LSB register (address 1Bh)

Table 43. DAC_B_AUX_MSB register (address 1Ch)

Table 44. DAC_B_AUX_LSB register (address 1Dh)

Table 45. DAC_B_AUX_LSB register (address 1Dh)

Table 46. Bias current control table . . . . . . . . . . . . . . . . . 46

Table 47. Page 1 register allocation map . . . . . . . . . . . . 47

Table 48. MDS_MAIN register (address 00h) bit

Table 49. MDS_WIN_PERIOD_A register

Table 50. MDS_WIN_PERIOD_B register

Table 51. MDS_MISCCNTRL0 register

Table 52. MDS_MAN_ADJUSTDLY register

Table 53. MDS_AUTO_CYCLES register

Table 54. MDS_MISCCNTRL1 register (address 06h)

Table 55. MDS_ADJDELAY register (address 08h) bit

Table 56. MDS_STATUS0 register (address 09h) bit

Table 57. MDS_STATUS1 register (address 0Ah) bit

Table 58. PAGE_ADDRESS register (address 1Fh)

Table 59. Page 2 register allocation map . . . . . . . . . . . . 52

2, 4 or 8 interpolating DAC with JESD204A

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

(address 16h) bit description . . . . . . . . . . . . . . 45

(address 17h) bit description . . . . . . . . . . . . . . 45

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

(address 01h) bit description . . . . . . . . . . . . . . 48

(address 02h) bit description . . . . . . . . . . . . . . 48

(address 03h) bit description . . . . . . . . . . . . . . 49

(address 04h) bit description . . . . . . . . . . . . . . 49

(address 05h) bit description . . . . . . . . . . . . . . 49

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51

DAC1008D750

continued >>

95 of 99

DAC1008D750HN/C1 NXP Semiconductors, DAC1008D750HN/C1 Datasheet - Page 95

DAC1008D750HN/C1

Specifications of DAC1008D750HN/C1

Related parts for DAC1008D750HN/C1