DAC1008D750HN/C1 NXP Semiconductors, DAC1008D750HN/C1 Datasheet - Page 14

• Manufacturer Part Number: DAC1008D750HN/C1
• Description: Digital to Analog Converters - DAC DL 10BIT DAC 750MSPS 2X 4X OR 8X INT
• Manufacturer: NXP Semiconductors

Specifications of DAC1008D750HN/C1

• Rohs: yes
• Factory Pack Quantity: 260

NXP Semiconductors
DAC1008D750
Product data sheet
Fig 5.
data in +
data in −
DC coupling
10.2.1 Lane input
10.2.2 Sync and word align
50 Ω
Each lane is CML compliant. It is terminated to a common voltage with an integrated 50 
resistor.
The common-mode voltage is programmable by the SET_VCM_VOLTAGE register as
shown in
DC coupling is only possible if both the DAC and the transmitter have the same
common-mode voltage. If this is not the case, AC coupling is required.
The deserializer performs the incoming data clock recovery and also the serial-to-parallel
conversion. Therefore, each lane includes its own PLL that must first lock.
The clock alignment module transfers the data from the regenerated clock to the frame
clock domain. The frequency of both clocks is the same but the phase relationship
between the clocks is unknown.
As stated in JESD204A, the transmitter and the receiver first have to synchronize. This is
achieved through the SYNC_OUT signals and a sync pattern (K28.5 symbol). The
receiver (i.e. DAC1008D750) first drives its SYNC_OUT outputs. The sync pattern is
continuously sent until the receiver deasserts the SYNC_OUT signal.
Fig 4.
50 Ω
Z diff = 100 Ω
Lane input termination
Table 75 on page
All information provided in this document is subject to legal disclaimers.
50 Ω
001aak162
Rev. 3 — 31 January 2012
50 Ω
56.
Vin_p
Vin_n
Fig 6.
2, 4 or 8 interpolating DAC with JESD204A
data in +
data in −
50 Ω
50 Ω
AC coupling
V
tt
Z tt
001aak166
V
50 Ω
DD1
50 Ω
DAC1008D750
Z diff = 100 Ω
© NXP B.V. 2012. All rights reserved.
V
50 Ω
DD2
001aak163
50 Ω
14 of 99