S29GL512S10FHI010 Spansion, S29GL512S10FHI010 Datasheet - Page 67

• Manufacturer Part Number: S29GL512S10FHI010
• Description: Flash 512Mb 3V 100ns Parallel NOR Flash
• Manufacturer: Spansion

Specifications of S29GL512S10FHI010

• Rohs: yes
• Data Bus Width: 16 bit
• Memory Type: Flash
• Memory Size: 512 Mbit
• Architecture: 32 M x 16
• Timing Type: Asynchronous
• Interface Type: Parallel
• Access Time: 100 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 25 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-64

10.4
10.5
10.6
May 30, 2008 S29GL-N_00_B8
DQ2: Toggle Bit II
Reading Toggle Bits DQ6/DQ2
DQ5: Exceeded Timing Limits
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode
information. Refer to
Figure 10.2 on page 66
on page 67
shows the toggle bit timing diagram.
graphical form.
Refer to
system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the
first read. After the second read, the system would compare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the program or erase operation. The system can read
array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or
erase operation. If it is still toggling, the device did not completed the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse
count limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not
successfully completed.
The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously
programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device
halts the operation, and when the timing limit is exceeded, DQ5 produces a 1.
In all these cases, the system must write the reset command to return the device to the reading the array (or
to erase-suspend-read if the device was previously in the erase-suspend-program mode).
Figure 10.2 on page 66
explains the algorithm. See also the
Table 10.1 on page 68
shows the toggle bit algorithm in flowchart form, and the section
D a t a
and
S h e e t
Figure 15.9 on page 78
Figure 15.9 on page 78
S29GL-N
to compare outputs for DQ2 and DQ6.
Figure 10.2 on page
RY/BY#: Ready/Busy# on page
shows the differences between DQ2 and DQ6 in
for the following discussion. Whenever the
66).
65.
Figure 15.8 on page 78
DQ2: Toggle Bit II
67