S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 155

• Manufacturer Part Number: S9S08SG8E2VTG
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTG

• Rohs: yes
• Core: S08
• Processor Series: MC9S08SG8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

10.1.4.4
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
10.1.4.5
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
10.1.4.6
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
10.1.4.7
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
10.2
There are no ICS signals that connect off chip.
10.3
Figure 10-1
Freescale Semiconductor
ICSTRM
ICSSC
ICSC1
ICSC2
Name
External Signal Description
Register Definition
is a summary of ICS registers.
FLL Bypassed Interna
FLL Bypassed Externa
FLL Bypassed Externa
Stop (STOP)
W
W
W
W
R
R
R
R
0
7
CLKS
BDIV
MC9S08SG8 MCU Series Data Sheet, Rev. 7
0
6
Table 10-1. ICS Register Summary
RANGE
0
5
l Low Power (FBILP)
l (FBE)
l Low Power (FBELP)
IREFST
RDIV
HGO
4
TRIM
LP
3
CLKST
EREFS
IREFS
2
Internal Clock Source (S08ICSV2)
ERCLKEN
IRCLKEN
OSCINIT
1
EREFSTEN
IREFSTEN
FTRIM
0
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