S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 242

• Manufacturer Part Number: S9S08SG8E2VTG
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTG

• Rohs: yes
• Core: S08
• Processor Series: MC9S08SG8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
16.1.4
In addition to
considerations when migrating from a device that uses TPMV1.
238
1
2
3
4
5
6
7
8
In Center-Aligned PWM mode when (CLKSB:CLKSA not =
00), writes to TPMxCnVH:L registers
Center-Aligned PWM
When TPMxCnVH:L = TPMxMODH:L
When TPMxCnVH:L = (TPMxMODH:L - 1)
TPMxCnVH:L is changed from 0x0000 to a non-zero value
TPMxCnVH:L is changed from a non-zero value to 0x0000
Write to TPMxMODH:L registers in BDM mode
In BDM mode, a write to TPMxSC register
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
•
You can write to the Channel Value register (TPMxCnV) when the timer is not in input capture
mode for TPMV2, not TPMV3.
Migrating from TPMV1
Section 16.1.3, “TPMV3 Differences from Previous
Table 16-2. TPMV2 and TPMV3 Porting Considerations (continued)
Action
Section 16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL)
Section 16.3.5, “TPM Channel Value Registers
Section 16.4.2.1, “Input Capture Mode
Section 16.4.2.4, “Center-Aligned PWM
Section 16.4.2.4, “Center-Aligned PWM
Section 16.4.2.4, “Center-Aligned PWM
Section 16.4.2.4, “Center-Aligned PWM
Section 16.4.2.4, “Center-Aligned PWM
4
5
MC9S08SG8 MCU Series Data Sheet, Rev. 7
6
7
8
Update the TPMxCnVH:L
registers with the value of
their write buffer after both
bytes are written and when
the TPM counter changes
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
0xFFFE to 0xFFFF.
Produces 100% duty cycle.
Produces a near 100% duty
cycle.
Waits for the start of a new
PWM period to begin using
the new duty cycle setting.
Finishes the current PWM
period using the old duty
cycle setting.
Clears the write coherency
mechanism of
TPMxMODH:L registers.
.”
Mode.”
Mode.” [SE110-TPM case 1]
Mode.” [SE110-TPM case 2]
Mode.” [SE110-TPM case 3 and 5]
Mode.” [SE110-TPM case 4]
TPMV3
Versions,” keep in mind the following
(TPMxCnVH:TPMxCnVL).”
Update after both bytes are
written and when the TPM
counter changes from
TPMxMODH:L to
(TPMxMODH:L - 1).
Produces 0% duty cycle.
Produces 0% duty cycle.
Changes the channel output at
the middle of the current PWM
period (when the count
reaches 0x0000).
Finishes the current PWM
period using the new duty
cycle setting.
Does not clear the write
coherency mechanism.
.” [SE110-TPM case 7]
Freescale Semiconductor
TPMV2