SC16IS762IBS-F NXP Semiconductors, SC16IS762IBS-F Datasheet - Page 21

• Manufacturer Part Number: SC16IS762IBS-F
• Description: UART Interface IC I2C/SPI-UARTBRIDGE W/IRDA AND GPIO
• Manufacturer: NXP Semiconductors
• Type: RS-232 or RS-485 or IrDAr

Specifications of SC16IS762IBS-F

• Product Category: UART Interface IC
• Rohs: yes
• Number Of Channels: 2
• Data Rate: 5 Mbps
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Package / Case: HVQFN-32
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Factory Pack Quantity: 1500
• Part # Aliases: SC16IS762IBS,128

Table 10.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Enhanced Features Registers are only accessible when LCR = 0xBF.
Register
address
Special register set
0x00
0x01
Enhanced register set
0x02
0x04
0x05
0x06
0x07
These registers are accessible only when LCR[7] = logic 0.
This bit can only be modified if register bit EFR[4] is enabled.
These bits are reserved and should be set to logic 0.
After Receive FIFO or Transmit FIFO reset (through FCR [1:0]), the user must wait at least 2  T
Burst reads on the serial interface (that is, reading multiple elements on the I
without de-asserting the CS pin), should not be performed on the IIR register.
These registers are accessible only when EFR[4] = logic 1, and MCR[2] = logic 1.
These registers apply to both channels.
IrDA mode slow/fast for SC16IS762, slow only for SC16IS752.
The Special Register set is accessible only when LCR[7] = logic 1 and LCR is not 0xBF.
SC16IS752/SC16IS762 internal registers
Register
DLL
DLH
EFR
XON1
XON2
XOFF1
XOFF2
[9]
[10]
Bit 7
bit 7
bit 7
Auto CTS
bit 7
bit 7
bit 7
bit 7
Bit 6
bit 6
bit 6
Auto RTS
bit 6
bit 6
bit 6
bit 6
…continued
Bit 5
bit 5
bit 5
special
character
detect
bit 5
bit 5
bit 5
bit 5
2
C-bus without a STOP or repeated START condition, or reading multiple elements on the SPI bus
Bit 4
bit 4
bit 4
enable
enhanced
functions
bit 4
bit 4
bit 4
bit 4
clk
Bit 3
bit 3
bit 3
software flow
control bit 3
bit 3
bit 3
bit 3
bit 3
of XTAL1 before reading or writing data to RHR and THR respectively.
Bit 2
bit 2
bit 2
software flow
control bit 2
bit 2
bit 2
bit 2
bit 2
Bit 1
bit 1
bit 1
software flow
control bit 1
bit 1
bit 1
bit 1
bit 1
Bit 0
bit 0
bit 0
software flow
control bit 0
bit 0
bit 0
bit 0
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W