C8051F707-GMR Silicon Labs, C8051F707-GMR Datasheet - Page 288

• Manufacturer Part Number: C8051F707-GMR
• Description: 8-bit Microcontrollers - MCU 16kB Cap Sense
• Manufacturer: Silicon Labs

Specifications of C8051F707-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F70x/71x
34.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun-
ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
288
Port I/O
hardware.
Crossbar
CEXn
Figure 34.4. PCA Capture Mode Diagram
W
M
P
1
6
n
x
PCA0CPMn
C
O
M
E
n
x
C
A
P
P
n
Rev. 1.0
C
N
A
P
n
0
1
M
A
T
n
0 0 0 x
O
G
T
n
W
M
P
n
C
C
E
F
n
0
1
C
F
C
R
PCA0CN
PCA
Timebase
C
C
F
2
C
C
F
1
C
C
F
0
PCA Interrupt
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H