DS3172N Maxim Integrated, DS3172N Datasheet - Page 111

• Manufacturer Part Number: DS3172N
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172N

• Part # Aliases: 90-31720-N00

10.12 LIU—Line Interface Unit
10.12.1 General Description
The line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3 or E3
lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. See
location within the DS317x device of the LIU.
Figure 10-31. LIU Functional Diagram
10.12.2 Features
•
•
•
•
•
•
•
10.12.2.1 Transmitter
•
•
•
•
•
•
•
•
10.12.2.2 Receiver
•
•
•
•
•
•
Clock Rate
Each Port Independently Configurable
Perform Receive Clock/Data Recovery and Transmit Waveshaping
Jitter Attenuators can be Placed in Either the Receive or Transmit Paths
Interface to 75Ω Coaxial Cable at Lengths Up to 380 meters (DS3), 440 meters (E3)
Use 1:2 Transformers on TX and RX
Require Minimal External Components
Local and Remote Loopbacks
Gapped clock capable up to 52MHz
Wide 50 ±20% transmit clock duty cycle
Clock inversion for glueless interfacing
Unframed all-ones generator (E3 AIS)
Line build-out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor
AGC/equalizer block handles from 0 to 15dB of cable loss
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Clock inversion for glueless interfacing
Per-channel power-down control
Receive
Transmit
DS3/E3
DS3/E3
Adapter
LIU
LIU
Encoder
Decoder
B3ZS/
HDB3
HDB3
B3ZS/
TUA1
TAIS
IEEE P1149.1
Access Port
JTAG Test
FEAC
DS3 / E3
DS3 / E3
Receive
Framer
Transmit
Formatter
Buffer
Trace
Trail
HDLC
GEN
UA1
111
RX BERT
TX BERT
Microprocessor
Interface
Figure 10-31
for the