DS3172N Maxim Integrated, DS3172N Datasheet - Page 176

• Manufacturer Part Number: DS3172N
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172N

• Part # Aliases: 90-31720-N00

12.9 DS3/E3 Framer
12.9.1 Transmit DS3
The transmit DS3 utilizes two registers.
Table 12-23. Transmit DS3 Framer Register Map
12.9.1.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 12: P-bit Generation Enable (PBGE) – When 0, Transmit Frame Processor P-bit generation is disabled. If
transmit frame generation is also disabled, the P-bit overhead periods in the incoming DS3 signal will be passed
through to overhead insertion. When 1, Transmit Frame Processor P-bit generation is enabled. The P-bit overhead
periods in the incoming DS3 signal will be overwritten even if transmit frame generation is disabled
Bit 11: Transmit DS3 Idle Signal (TIDLE) –
Bit 10: C-bit Generation Disable (CBGD) (M23 mode only) – When 0, Transmit Frame Processor C-bit
generation is enabled. The C-bit overhead periods in the incoming M23 DS3 signal will be overwritten with zeros.
When 1, Transmit Frame Processor C-bit generation is disabled. The C-bit overhead periods in the incoming M23
DS3 signal will be treated as payload, and passed through to overhead insertion. This bit is ignored in C-bit DS3
mode.
Bit 5: Transmit FEBE Error (TFEBE) – When automatic far-end block error generation is defeated (AFEBED = 1),
the inverse of this bit is inserted into the bits C
indicates a far-end block error. This bit is ignored in M23 DS3 mode.
Bit 4: Automatic FEBE Defeat (AFEBED) – When 0, a far-end block error is automatically generated based upon
the receive C-bit parity errors or framing errors. When 1, a far-end block error is inserted from the register bit
TFEBE. This bit is ignored in M23 DS3 mode.
Bit 3: Transmit RDI Alarm (TRDI) – When automatic RDI generation is defeated (ARDID = 1), the inverse of this
bit is inserted into the X-bits (X
(1,3,5,7)1Ch
(1,3,5,7)1Ah T3.TEIR
(1,3,5,7)1Eh
(1,3,5,7)18h T3.TCR
Address
0 = Transmit DS3 Idle signal is not inserted
1 = Transmit DS3 Idle signal is inserted into the DS3 frame.
15
--
--
0
7
0
Register
--
--
14
--
--
0
6
0
1
T3 Transmit Control Register
T3 Transmit Error Insertion Register
Reserved
Reserved
and X
Register Description
T3.TCR
T3 Transmit Control Register
(1,3,5,7)18h
2
). Note: an RDI value of zero (TRDI=1) indicates an alarm.
TFEBE
13
--
0
5
0
41
, C
42
AFEBED
PBGE
, and C
12
0
0
4
176
43
. Note: a far-end block error value of zero (TFEBE=1)
TIDLE
TRDI
11
0
3
0
ARDID
CBGD
10
0
2
0
TFGC
--
9
0
1
0
TAIS
--
8
0
0
0