DS3172N Maxim Integrated, DS3172N Datasheet - Page 131

• Manufacturer Part Number: DS3172N
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172N

• Part # Aliases: 90-31720-N00

Bits 1 to 0: General-Purpose IO 1 Select [1:0] (GPIO1S[1:0]). These bits determine the function of the GPIO1
pin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bits 7 to 4: Port Interrupt Status Register [4:1] (PISR[4:1] ) The corresponding bit is set when any of the bits in
the port interrupt status registers (PORT.ISR) are set. The INT interrupt pin will be driven low when any bit is set
and the corresponding GL.ISRIE.PISRIE[4:1] interrupt enable bit is enabled.
Bit 0: Global Status Register Interrupt Status (GSR) This bit is set when any of the latched status register bits in
the global latched status register (GL.SRL) are set and enabled for interrupt. The INT interrupt pin will be driven low
when this bit is set and the GL.ISRIE.GSRIE interrupt enable bit is enabled.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 4: Port Interrupt Status Register Interrupt Enable [4:1] (PISRIE[4:1]) When any interrupt enable bit in
this group is enabled corresponding to a status bit set in the GL.ISR.PISR[4:1] status bit group, the INT pin will be
driven low.
Bit 0: Global Status Register Interrupt Status Interrupt Enable (GSRIE) When this interrupt enable bit is
enabled, and the GL.ISR.GSR status bit is set, the INT pin will be driven low.
11 = Output logic 1
00 = Input
01 = Port 1 A status output selected by PORT.CR4:GPIOA[3:0] in port control registers
10 = Output logic 0
11 = Output logic 1
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
PISRIE4
PISR4
15
15
--
--
7
0
7
0
PISRIE3
PISR3
14
14
--
--
6
0
6
0
GL.ISR
Global Interrupt Status Register
010h
GL.ISRIE
Global Interrupt Status Register Interrupt Enable
012h
PISRIE2
PISR2
13
13
--
--
5
0
5
0
PISRIE1
PISR1
12
12
--
--
0
0
4
4
131
11
11
--
--
--
--
3
0
3
0
10
10
--
--
--
--
2
0
2
0
RESERVED
RESERVED
--
--
9
1
9
0
1
0
GSRIE
GSR
--
--
8
0
8
0
0
0