DS3172N Maxim Integrated, DS3172N Datasheet - Page 206
![no-image](/images/no-image-200.jpg)
DS3172N
Manufacturer Part Number
DS3172N
Description
Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
Manufacturer
Maxim Integrated
Datasheet
1.DS3171.pdf
(234 pages)
Specifications of DS3172N
Part # Aliases
90-31720-N00
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Framing Error Count (FE[15:0]) – These sixteen bits indicate the number of framing error events on
the incoming E3 data stream. This register is updated via the PMU signal (see Section 10.4.5).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Parity Error Count (PE[15:0]) – These sixteen bits indicate the number of parity (BIP-8) errors
detected on the incoming E3 data stream. This register is updated via the PMU signal (see Section 10.4.5).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Remote Error Indication Count (FBE[15:0]) – These sixteen bits indicate the number of remote
error indications detected on the incoming E3 data stream. This register is updated via the PMU signal (see
Section 10.4.5).
FBE15
FBE7
FE15
PE15
FE7
PE7
15
15
15
0
7
0
0
7
0
0
7
0
FBE14
FBE6
FE14
PE14
PE6
FE6
14
14
14
0
6
0
0
6
0
0
6
0
E3G832.RFECR
E3 G.832 Receive Framing Error Count Register
(1,3,5,7)34h
E3G832.RPECR
E3 G.832 Receive Parity Error Count Register
(1,3,5,7)36h
E3G832.RFBER
E3 G.832 Receive Remote Error Indication Count Register
(1,3,5,7)38h
FBE13
PE13
FBE5
FE13
PE5
FE5
13
13
13
0
5
0
0
5
0
0
5
0
FBE12
FBE4
FE12
PE12
FE4
PE4
12
12
12
0
0
0
0
0
0
4
4
4
206
FBE11
PE11
FBE3
FE11
PE3
FE3
11
11
11
0
3
0
0
3
0
0
3
0
FBE10
FE10
PE10
FBE2
FE2
PE2
10
10
10
0
2
0
0
2
0
0
2
0
FBE9
FBE1
FE9
FE1
PE9
PE1
9
0
1
0
9
0
1
0
9
0
1
0
FBE8
FBE0
PE8
PE0
FE8
FE0
8
0
0
0
8
0
0
0
8
0
0
0
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