72V3644L10PF IDT, 72V3644L10PF Datasheet
72V3644L10PF
Specifications of 72V3644L10PF
Related parts for 72V3644L10PF
72V3644L10PF Summary of contents
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... EFA/ORA AEA 36 MBF2 IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 3.3 VOLT CMOS SyncBiFIFO ...
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... DESCRIPTION: The IDT72V3624/72V3634/72V3644 are pin and functionally compatible versions of the IDT723624/723634/723644, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, high- speed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory ...
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... COMMERCIAL TEMPERATURE RANGE EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB). The EF and FF functions are selected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the memory is full or not. The IR and OR functions are selected in the First Word Fall Through mode ...
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... FWFT must be static throughout device operation. BM Bus-Match I A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A Select LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian (Port B) arrangement for Port B ...
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... IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O FS1/SEN Flag Offset Select 1/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset ...
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... IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I V (2) Output Voltage Range O I Input Clamp Current ( Output Clamp Current (V ...
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... DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3624/72V3634/72V3644 with CC(f) CLKA and CLKB set All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were S disconnected to normalize the graph to a zero capacitance load ...
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... IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Commercial 3.3V +/- 0.30V; for 10ns (100 MHz operation Symbol Parameter f Clock Frequency, CLKA or CLKB S t Clock Cycle Time, CLKA or CLKB ...
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... IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C Commercial 3.3V +/- 0.30V; for 10ns (100 MHz operation Symbol Parameter t Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 A Propagation Delay Time, CLKA↑ ...
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... FIFO is ready to be written to. Whatever flag offsets, programming method (parallel or serial), and timing mode (FWFT or IDT Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will be remain unchanged upon completion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be inconvenient ...
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... Valid programming values for the registers range from 1 to 252 for the IDT72V3624 508 for the IDT72V3634; and 1 to 1,020 for the IDT72V3644. After all the offset registers are programmed from Port A, the Port B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal operation ...
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... Chip Select, Write/Read select, Enable, and Mailbox select. When operating the FIFO in IDT Standard mode, the first word will cause the Empty Flag to change state on the second LOW-to-HIGH transition of the Read Clock. The data word will not be automatically sent to the output register. ...
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... X1 is the Almost-Empty offset for FIFO1 used by AEB the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming. 4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode. ...
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... A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2 Register when a Port B write is selected by CSB, W/RB, and ENB with MBB HIGH. If the selected Port B bus size is also 36 bits, then the usable width of the Mail2 employs data lines B0-B35. If the selected Port B bus size is 18 bits, then the usable width of the Mail2 Register employs data lines B0-B17. (In this case, B18-B35 are don’ ...
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... RAM. These bus-matching operations are not available when transferring data via mailbox registers. Furthermore, both the word- and byte-size bus selections limit the width of the data bus that can be used for mail register operations. In this case, only those byte lanes belonging to the selected word- or byte-size bus can carry mailbox data. The remaining data outputs will be indeterminate. The remaining data inputs will be don’ ...
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... IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 BYTE ORDER ON PORT A: BYTE ORDER ON PORT SIZE SIZE SIZE SIZE SIZE WITH BUS-MATCHING A35 A27 A26 A18 A17 A9 ...
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... Figure 4. FIFO1 Partial Reset TM WITH BUS-MATCHING t RSTH t BES BE t SPMS t FSS 0,1 t WFF (3) t REF t RSTH t WFF t REF (3) (1) (IDT Standard and FWFT Modes) 17 COMMERCIAL TEMPERATURE RANGE t BEH t FWS FWFT t SPMH t FSH t WFF 4664 drw05 (1) (IDT Standard and FWFT Modes) t WFF 4664 drw06 ...
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... FFB/IRB may transition HIGH one CLKB cycle later than shown. edge of CLKB is less than t SKEW1 2. CSA=LOW, W/RA=HIGH,MBA=LOW not necessary to program offset register on consecutive clock cycles. Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes) CLKA 4 MRS1, ...
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... DATA SIZE TABLE FOR LONG-WORD WRITES TO FIFO2 (1) SIZE MODE BM SIZE BE B35-B27 NOTE selected at Master Reset: BM and SIZE must be static throughout device operation. Figure 8. Port B Long-Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes) TM WITH BUS-MATCHING t ENH t ENH t ENH t t ENS2 ENH ...
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... DATA SIZE TABLE FOR BYTE WRITES TO FIFO2 (1) SIZE MODE BM SIZE NOTE selected at Master Reset; BM and SIZE must be static throughout device operation. Figure 10. Port B Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes) TM WITH BUS-MATCHING t ENS1 t ENS2 t t ENS2 t ENS2 ENH t ...
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... DATA SIZE TABLE FOR FIFO LONG-WORD READS FROM FIFO1 (1) SIZE MODE BM SIZE BE A35-A27 NOTE selected at Master Reset; BM and SIZE must be static throughout device operation . Figure 11. Port B Long-Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes) CLKB EFB/ORB HIGH CSB W/RB MBB ENB B0-B17 (Standard Mode) OR B0-B17 ...
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... DATA SIZE TABLE FOR BYTE READS FROM FIFO1 (1) SIZE MODE BM SIZE NOTE selected at Master Reset; BM and SIZE must be static throughout device operation. Figure 13. Port-B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes) t CLK t CLKH CLKA EFA/ORA HIGH CSA W/RA MBA ENA t t ...
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... IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKA CSA LOW W/RA HIGH t t ENS2 ENH MBA t t ENS2 ENH ENA IRA HIGH A0-A35 W1 t SKEW1 CLKB ORB FIFO1 Empty CSB LOW W/RB HIGH LOW MBB ENB ...
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... CLKB edge is less than t SKEW1 2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively. Figure 16. EFB EFB EFB EFB EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode) TM WITH BUS-MATCHING t CLK t t ...
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... IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH B0-B35 t SKEW1 CLKA ORA FIFO2 Empty CSA LOW W/RA LOW MBA LOW ENA A0-A35 ...
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... SKEW1 2. If Port B size is word or byte referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. SKEW1 Figure 18. EFA EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode) EFA EFA EFA TM ...
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... If Port B size is word or byte referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively. SKEW1 Figure 20. FFA FFA FFA FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode) FFA TM WITH BUS-MATCHING t ENH ...
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... IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW W/RA LOW LOW MBA t ENS2 ENA ORA HIGH A0-A35 Previous Word in FIFO2 Output Register CLKB IRB FIFO2 FULL CSB LOW W/RB LOW MBB ENB ...
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... CLKB edge is less than t SKEW1 2. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively. Figure 22. FFB FFB FFB FFB FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode) TM WITH BUS-MATCHING t ENH t A ...
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... FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO Maximum FIFO Depth = 256 for the IDT72V3624, 512 for the IDT72V3634, 1,024 for the IDT72V3644. ...
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... FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO Maximum FIFO Depth = 256 for the IDT72V3624, 512 for the IDT72V3634, 1,024 for the IDT72V3644. ...
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... Figure 28. Timing for Mail2 Register and MBF2 TM WITH BUS-MATCHING t ENH t ENH t ENH t ENH PMF t PMR t MDV W1 (Remains valid in Mail 2 Register after read) MBF2 MBF2 Flag (IDT Standard and FWFT Modes) MBF2 MBF2 32 COMMERCIAL TEMPERATURE RANGE t PMF t ENH t ENS2 t DIS 4664 drw30 ...
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... IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO 256 512 1,024 PARAMETER MEASUREMENT INFORMATION From Output Under Test Timing 1.5V Input Data, 1.5V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5V t PZL t PLZ Low-Level Output t PZH High-Level Output ...
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... SyncBiFIFO 72V3634 72V3644 1,024 ⎯ 3.3V SyncBiFIFO for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 34 Clock Cycle Time (t ) CLK Speed in Nanoseconds ™ with Bus-Matching ™ with Bus-Matching ™ with Bus-Matching 4664 drw32 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ...