72V3644L10PF IDT, 72V3644L10PF Datasheet - Page 27

• Manufacturer Part Number: 72V3644L10PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V3644L10PF

• Part # Aliases: IDT72V3644L10PF

NOTES:
1. t
2. If Port B size is word or byte, t
NOTES:
1. t
2. If Port B size is word or byte, t
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKA edge is less than t
CLKA edge is less than t
SKEW1
SKEW1
B0-B35
A0-A35
CLKB
B0-B35
A0-A35
W/RB
CLKA
W/RA
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
MBB
ENB
ORB
MBA
CSB
ENA
CSA
CLKA
CLKB
W/RB
W/RA
IRA
MBB
MBA
CSB
ENA
ENB
CSA
EFB
FFA
FIFO1 Full
LOW
LOW
HIGH
LOW
HIGH
HIGH
Previous Word in FIFO1 Output Register
LOW
LOW
HIGH
FIFO1 Full
HIGH
LOW
HIGH
Previous Word in FIFO1 Output Register
SKEW1
SKEW1
t
CLKH
Figure 20. FFA
t
SKEW1
CLKH
SKEW1
, then IRA may transition HIGH one CLKA cycle later than shown.
, then FFA may transition HIGH one CLKA cycle later than shown.
Figure 19. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
t
CLK
is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
t
t
CLK
ENS2
t
ENS2
t
CLKL
FFA
FFA
FFA
FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
t
CLKL
t
t
SKEW1
ENH
t
A
t
t
SKEW1
ENH
t
A
(1)
(1)
1
t
TM
CLKH
1
WITH BUS-MATCHING
t
CLKH
t
CLK
t
27
CLK
t
CLKL
t
CLKL
2
2
Next Word From FIFO1
t
WFF
Next Word From FIFO1
t
WFF
t
t
ENS2
ENS2
t
t
ENS2
t
ENS2
DS
t
DS
To FIFO1
To FIFO1
COMMERCIAL TEMPERATURE RANGE
Write
Write
t
t
t
WFF
t
ENH
DH
ENH
t
t
WFF
t
DH
t
ENH
ENH
4664 drw21
4664 drw22