72V3644L10PF IDT, 72V3644L10PF Datasheet - Page 26

• Manufacturer Part Number: 72V3644L10PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V3644L10PF

• Part # Aliases: IDT72V3644L10PF

NOTES:
1. t
2. If Port B size is word or byte, t
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
A0-A35
B0-B35
CLKA edge is less than t
CLKA
W/RA
CLKB
W/RB
SKEW1
MBB
MBA
CSB
ENA
ENB
CSA
EFA
FFB
is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
LOW
SKEW1
t
t
ENS2
ENS2
t
Figure 18. EFA
DS
SKEW1
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
W1
EFA
EFA
EFA
EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
t
SKEW1
t
t
t
ENH
ENH
DH
(1)
t
CLKH
1
t
CLK
t
TM
CLKL
WITH BUS-MATCHING
26
t
REF
2
t
CLKH
t
ENS2
t
CLK
t
CLKL
t
REF
t
A
t
ENH
COMMERCIAL TEMPERATURE RANGE
W1
4664 drw20