72V3644L10PF IDT, 72V3644L10PF Datasheet - Page 7

• Manufacturer Part Number: 72V3644L10PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V3644L10PF

• Part # Aliases: IDT72V3644L10PF

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
CLKA and CLKB set to f
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
The I
With I
200
175
100
150
125
75
50
25
0
CC(f)
P
where:
N
C
f
o
CC(f)
T
L
0
= V
current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3624/72V3634/72V3644 with
taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
CC
=
=
=
x I
CC
S
. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
10
(f) + Σ(C
f
data
T
C
A
L
= 25
N
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
output capacitance load
switching frequency of an output
= 0 pF
Figure 1. Typical Characteristics: Supply Current (I
= 1/2 f
L
ο
x V
C
S
20
CC
2
V
x fo)
CC
= 3.3V
30
f
S
Clock Frequency MHz
TM
40
WITH BUS-MATCHING
7
50
CC
V
) vs. Clock Frequency (f
CC
60
= 3.6V
70
COMMERCIAL TEMPERATURE RANGE
V
CC
= 3.0V
S
)
80
90
4664 drw03
100