72V3644L10PF IDT, 72V3644L10PF Datasheet - Page 10

• Manufacturer Part Number: 72V3644L10PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V3644L10PF

• Part # Aliases: IDT72V3644L10PF

SIGNAL DESCRIPTION
MASTER RESET (MRS1, MRS2)
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, each of the two
FIFO memories of the IDT72V3624/72V3634/72V3644 undergoes a complete
reset by taking its associated Master Reset (MRS1, MRS2) input LOW for at
least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH
transitions. The Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the associated write and read pointers to the first
location of the memory and forces the Full/Input Ready flag (FFA/IRA, FFB/
IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost-Empty flag (AEA, AEB) LOW and forces the Almost-Full flag (AFA, AFB)
HIGH. A Master Reset also forces the associated Mailbox Flag (MBF1, MFB2)
of the parallel mailbox register HIGH. After a Master Reset, the FIFO's Full/
Input Ready flag is set HIGH after two write clock cycles. Then the FIFO is ready
to be written to.
latches the values of the Big-Endian (BE) input for determining the order by
which bytes are transferred through Port B. It also latches the values of the
Flag Select (FS0, FS1) and Serial Programming Mode (SPM) inputs for
choosing the Almost-Full and Almost-Empty offset programming method.
Flag Offset Registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the
FIFO2 Master Reset (MRS2) together with the FIFO1 Master Reset (MRS1)
input latches the value of the Big-Endian (BE) input for Port B and also latches
the values of the Flag Select (FS0, FS1) and Serial Programming Mode (SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method. (For details see Table 1, Flag Programming, and the Programming
the Almost-Empty and Almost-Full Flags section). The relevant FIFO Master
Reset timing diagram can be found in Figure 3.
PARTIAL RESET (PRS1, PRS2)
by taking its associated Partial Reset (PRS1, PRS2) input LOW for at least four
Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions.
The Partial Reset inputs can switch asynchronously to the clocks. A Partial
Reset initializes the internal read and write pointers and forces the Full/Input
Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/
ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the
Almost-Full flag (AFA, AFB) HIGH. A Partial Reset also forces the Mailbox Flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a Partial Reset, the
FIFO’s Full/Input Ready flag is set HIGH after two write clock cycles. Then
the FIFO is ready to be written to.
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be inconvenient. See
Figure 4 for the Partial Reset timing diagram.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
— ENDIAN SELECTION
is active, permitting a choice of Big or Little-Endian byte arrangement for data
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
unused inputs) must not be left open, rather they must be either HIGH or LOW.
Each of the two FIFO memories of these devices undergoes a limited reset
Whatever flag offsets, programming method (parallel or serial), and timing
This is a dual purpose pin. At the time of Master Reset, the BE select function
After power up, a Master Reset operation must be performed by providing
A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input
A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) clears the
TM
WITH BUS-MATCHING
10
written to or read from Port B. This selection determines the order by which bytes
(or words) of data are transferred through this port. For the following
illustrations, assume that a byte (or word) bus size has been selected for Port
B. (Note that when Port B is configured for a long word size, the Big-Endian
function has no application and the BE input is a “don’t care”
inputs go from LOW to HIGH will select a Big-Endian arrangement. When data
is moving in the direction from Port A to Port B, the most significant byte (word)
of the long word written to Port A will be read from Port B first; the least significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written to
Port B first will be read from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port B last will be read from Port A as the least
significant byte (word) of the long word.
inputs go from LOW to HIGH will select a Little-Endian arrangement. When data
is moving in the direction from Port A to Port B, the least significant byte (word)
of the long word written to Port A will be read from Port B first; the most significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written to
Port B first will be read from Port A as the least significant byte (word) of the long
word; the byte (word) written to Port B last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figure 2 for an illustration of
the BE function. See Figure 3 (Master Reset) for the Endian select timing
diagram.
— TIMING MODE SELECTION
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (MRS1, MRS2) input is HIGH,
a HIGH on the BE/FWFT input during the next LOW-to-HIGH transition of CLKA
(for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (EFA, EFB) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag function (FFA,
FFB) to indicate whether or not the FIFO memory has any free space for writing.
In IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.
FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and
CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB)
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.
the desired timing mode must remain static throughout FIFO operation. Refer
to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
offset values for the Almost-Empty and Almost-Full flags. The Port B Almost-
Empty flag (AEB) Offset register is labeled X1 and the Port A Almost-Empty flag
(AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA) Offset
register is labeled Y1 and the Port B Almost-Full flag (AFB) Offset register is
A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2)
A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2)
After Master Reset, the FWFT select function is active, permitting a choice
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/
Following Master Reset, the level applied to the BE/FWFT input to choose
Four registers in the IDT72V3624/72V3634/72V3644 are used to hold the
COMMERCIAL TEMPERATURE RANGE
1
.)