P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet

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... Four I C controllers • Four 2-pin UARTs or two 4-pin UARTs Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2013 Freescale Semiconductor, Inc. All rights reserved. Document Number: P5020EC P5020/P5010 FC-PBGA–1295 37.5 mm × 37.5 mm • ...

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... Thermal Management Information . . . . . . . . . . . . . . 157 4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 4.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 158 4.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 159 5 Security Fuse Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.1 Part Numbering Nomenclature . . . . . . . . . . . . . . . . . 160 6.2 Orderable Part Numbers Addressed by this Document161 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Block Power Supply Decoupling Freescale Semiconductor ...

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... DUART 2 USB 2.0 RAID + 2x PHY sRIO 5/6 Mgr Clocks/Reset Engine GPIO P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Power Architecture® e5500 Core 512-Kbyte Backside L2 Cache 32-Kbyte 32-Kbyte D-Cache I-Cache CoreNet™ Coherency Fabric PAMU Frame Manager Parse, Classify, ...

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... SERDES Figure 2. Preliminary P5010 Block Diagram 1024-Kbyte 64-bit Frontside DDR3/DDR3L CoreNet Memory Platform Controller Cache PAMU Real Time Debug Watchpoint DMA DMA Cross Trigger Perf CoreNet Monitor PCIe PCIe PCIe/ PCIe sRIO Aurora Freescale Semiconductor Trace ...

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... I/O Supply Voltage LV DD I/O Supply Voltage GV DD DDR DRAM I/O Supply CV DD SPI Voltage Supply BV DD Local Bus I/O Supply Figure 3. P5020—1295 BGA Ball Map Diagram (Top View) P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor D2_ ...

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... GND VDD_PL GND VDD_PL GND VDD_PL [124] [31] [138] [77] [154] [90] VDD_PL GND VDD_PL GND VDD_PL GND [16] [130] [61] [145] [22] [222] Freescale Semiconductor 18 GND [24] GND [31 [4] NC [D18] LAD [28] LAD [29] LA [31 [9] LAD [13] LAD [14] GND [32] VDD_CA [17] GND [160] VDD_CA [18] ...

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... GND VDD_PL GND VDD_PL GND VDD_PL [175] [28] [190] [30] [205] [41] Figure 5. P5020—1295 BGA Ball Map Diagram (Detail View B) P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor SGND SD_RX RSRV GND [A27] [1] [1] [1] [A25] [23] SD_IMP_ ...

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... MDQ MDQ MDVAL HRESET [92] [59] [62] [59] D1_ D1_ RESET_ MDQS MDQ POVDD [AT14] [9] REQ [7] [58 Freescale Semiconductor GND [167] VDD_CB [13] GND [169] VDD_CB [14] GND [168] VDD_PL [95] GND [170] VDD_PL [60] GND [79] MSRCID [ [3] IO_ VSEL [2] IO_ VSEL ...

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... AVDD_ TEST_ SYSCLK DAT [AT19] PLAT [93] SEL [ Figure 7. P5020—1295 BGA Ball Map Diagram (Detail View D) P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor DETAIL VDD_PL GND VDD_PL [W27] [48] [109] [53] [32] NC SD_TX GND VDD_PL GND ...

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... DD F16 I/O GV — DD E15 I/O GV — DD E13 I/O GV — DD F13 I/O GV — I/O GV — DD D12 I/O GV — I/O GV — DD E10 I/O GV — DD C11 I/O GV — DD C10 I/O GV — I/O GV — I/O GV — I/O GV — DD F11 I/O GV — DD H10 I/O GV — DD J10 I/O GV — DD F10 I/O GV — I/O GV — I/O GV — DD Freescale Semiconductor ...

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... D1_MDQ52 D1_MDQ53 D1_MDQ54 D1_MDQ55 D1_MDQ56 D1_MDQ57 D1_MDQ58 D1_MDQ59 D1_MDQ60 D1_MDQ61 D1_MDQ62 D1_MDQ63 D1_MECC0 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Data Data Data Data Data Data Data Data Data Data Data Data ...

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... DD AT10 O GV — — DD C16 I/O GV — DD G14 I/O GV — I/O GV — I/O GV — DD AD5 I/O GV — DD AH6 I/O GV — DD AM10 I/O GV — DD AT12 I/O GV — I/O GV — DD B16 I/O GV — DD F14 I/O GV — I/O GV — I/O GV — DD AD4 I/O GV — DD AH5 I/O GV — DD AM9 I/O GV — DD Freescale Semiconductor ...

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... D1_MCAS D1_MCS0 D1_MCS1 D1_MCS2 D1_MCS3 D1_MCKE0 D1_MCKE1 D1_MCKE2 D1_MCKE3 D1_MCK0 D1_MCK1 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Data Strobe Data Strobe Bank Select Bank Select Bank Select Address Address Address Address ...

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... A13 I B13 I B10 Freescale Semiconductor ...

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... D2_MDQ42 D2_MDQ43 D2_MDQ44 D2_MDQ45 D2_MDQ46 D2_MDQ47 D2_MDQ48 D2_MDQ49 D2_MDQ50 D2_MDQ51 D2_MDQ52 D2_MDQ53 D2_MDQ54 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Data Data Data Data Data Data Data Data Data Data Data Data ...

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... B12 AG1 AL3 AP2 AP6 A10 AH2 I AM4 I Freescale Semiconductor ...

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... D2_MA10 D2_MA11 D2_MA12 D2_MA13 D2_MA14 D2_MA15 D2_MWE D2_MRAS D2_MCAS P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe ...

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... AD2 AF1 AD1 AE3 AA4 I/O GV 16, I/O GV 16,34 DD K26 I L26 I J26 I H25 I F25 I H24 I G24 I G23 I E23 I D23 I J22 I Freescale Semiconductor ...

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... LA27 LA28 LA29 LA30 LA31 LCS0 LCS1 LCS2 LCS3 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Muxed Data/Address Muxed Data/Address Muxed Data/Address Muxed Data/Address Muxed Data/Address Muxed Data/Address Muxed Data/Address Muxed Data/Address ...

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... C25 I E26 C24 O BV — DD C23 O BV — DD AP21 AL19 AN21 AJ20 AG19 AP20 AT27 I/O USB_V — D _3P3 D AT26 I/O USB_V — D _3P3 D Freescale Semiconductor ...

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... IRQ06/GPIO24 IRQ07/GPIO25 IRQ08/GPIO26 IRQ09/GPIO27 IRQ10/GPIO28 IRQ11/GPIO29 IRQ_OUT/EVT9 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description USB1 PHY VBUS Divided Signal USB1 PHY ID Detect USB1 5V Supply Enable USB1 Power Fault USB PHY Clock Input ...

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... AK29 O CV — DD AN29 AJ28 AR29 AM29 AL35 I LV — DD AL36 I LV — DD AK36 I LV — DD AJ36 O LV — DD AK35 AM30 O LV — DD AL30 O LV — DD AJ34 Freescale Semiconductor ...

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... EC1_RXD0 EC1_RX_DV EC1_RX_CLK EC1_RX_ER/TSEC_1588_TRIG_IN2 EC1_COL/GPIO30/TSEC_1588_ALARM_OUT2 EC1_CRS/GPIO31/TSEC_1588_PULSE_OUT2 EC2_TXD3 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Management Data Clock Management Data In/Out Ethernet Management Interface 2 Management Data Clock Management Data In/Out Ethernet Reference Clock ...

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... AN23 AM22 AK23 AP22 AH23 AH15 I AN14 I AM15 I AL14 I AK13 I 14 AM14 I 14 AG14 I AL15 I Freescale Semiconductor ...

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... SD_TX08 SD_TX07 SD_TX06 SD_TX05 SD_TX04 SD_TX03 SD_TX02 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Transmit Data (positive) Transmit Data (positive) Transmit Data (positive) Transmit Data (positive) Transmit Data (positive) Transmit Data (positive) ...

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... AF33 I XV — DD AC35 I XV — DD AA35 I XV — DD Y33 I XV — DD W35 I XV — DD T33 I XV — DD P35 I XV — DD M35 I XV — DD L33 I XV — DD K35 I XV — DD H35 I XV — DD F35 I XV — DD C36 I XV — DD Freescale Semiconductor ...

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... GPIO11/UART2_SIN GPIO12/UART1_RTS/UART3_SOUT GPIO13/UART2_RTS/UART4_SOUT GPIO14/UART1_CTS/UART3_SIN GPIO15/UART2_CTS/UART4_SIN GPIO16/IIC3_SCL/SDHC_CD GPIO17/IIC3_SDA/SDHC_WP GPIO18/DMA1_DREQ0 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Receive Data (negative) Receive Data (negative) Receive Data (negative) Receive Data (negative) SerDes Bank 1 PLL Reference Clock ...

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... AM19 AJ17 I AK17 I/O OV — DD AN16 I/O OV — DD AK16 I/O OV — DD AM16 I/O OV — DD AG14 I/O OV — DD AL15 I/O OV — DD AG19 I/O OV — DD AP20 I/O OV — DD AK14 I/O OV — DD AR15 O OV — DD AH20 20 AJ19 O OV — DD AH18 O OV — DD AJ20 Freescale Semiconductor ...

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... GND GND GND GND GND GND GND GND P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Alternate Debug Source ID 0 Alternate Debug Source ID 1 Clock Out Clock Real Time Clock System Clock JTAG ...

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... L18 — — — J21 — — — M27 — — — G13 — — — F15 — — — H11 — — — J9 — — — K7 — — — L5 — — — M3 — — — R3 — — — Freescale Semiconductor ...

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... GND GND GND GND GND GND GND GND GND GND GND GND GND P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground ...

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... AH34 — — — AT36 — — — AL34 — — — AM32 — — — AE26 — — — AC26 — — — AA26 — — — W26 — — — U26 — — — Freescale Semiconductor ...

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... GND GND GND GND GND GND GND GND GND GND GND GND GND P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground ...

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... AE18 — — — AF19 — — — AD19 — — — AB19 — — — Y19 — — — V19 — — — T19 — — — P19 — — — M19 — — — Freescale Semiconductor ...

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... GND GND GND GND GND GND GND GND GND GND GND GND GND P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground ...

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... AG30 — — — D33 — — — E28 — — — E30 — — — F32 — — — G29 — — — G31 — — — H29 — — — H32 — — — Freescale Semiconductor ...

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... SGND SGND SGND SGND SGND SGND SGND P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description SerDes Transceiver GND SerDes Transceiver GND SerDes Transceiver GND SerDes Transceiver GND SerDes Transceiver GND SerDes Transceiver GND ...

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... K27 — — 8 K17 — — 8 AG16 — — 8 AH24 — — — AJ24 — — — AL25 — — — AM25 — — — AR25 — — — AR26 — — — AR27 — — — Freescale Semiconductor ...

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... GVDD GVDD GVDD GVDD GVDD GVDD P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description USB1 PHY Transceiver GND USB1 PHY Transceiver GND USB1 PHY Transceiver GND USB2 PHY Transceiver GND USB2 PHY Transceiver GND ...

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... N10 — GV — — GV — — GV — — GV — DD T10 — GV — — GV — DD J12 — GV — — GV — — GV — — GV — DD AK10 — GV — DD W10 — GV — DD AA6 — GV — DD Freescale Semiconductor ...

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... GVDD GVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description DDR Supply DDR Supply DDR Supply DDR Supply DDR Supply DDR Supply DDR Supply DDR Supply ...

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... K34 — SV — DD L35 — SV — DD M33 — SV — DD N36 — SV — DD R34 — SV — DD R35 — SV — DD U33 — SV — DD V35 — SV — DD W34 — SV — DD Y36 — SV — DD AH36 — SV — DD AA29 — XV — DD AB30 — XV — DD Freescale Semiconductor ...

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... XVDD XVDD XVDD XVDD XVDD LVDD LVDD P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description SerDes Transceiver Supply SerDes Transceiver Supply SerDes Transceiver Supply SerDes Transceiver Supply SerDes Transceiver Supply SerDes Transceiver Supply ...

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... V — DD_PL AD12 — V — DD_PL AE13 — V — DD_PL AE15 — V — DD_PL V16 — V — DD_PL AE17 — V — DD_PL L11 — V — DD_PL AE19 — V — DD_PL U11 — V — DD_PL AC11 — V — DD_PL Freescale Semiconductor ...

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... VDD_PL VDD_PL VDD_PL VDD_PL VDD_PL VDD_PL VDD_PL VDD_PL VDD_PL P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Platform Supply Platform Supply Platform Supply Platform Supply Platform Supply Platform Supply Platform Supply Platform Supply ...

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... V — DD_PL AA13 — V — DD_PL R13 — V — DD_PL M14 — V — DD_PL U17 — V — DD_PL U19 — V — DD_PL T14 — V — DD_PL AD14 — V — DD_PL AD16 — V — DD_PL AD18 — V — DD_PL Freescale Semiconductor ...

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... VDD_CB VDD_CB VDD_CB VDD_CB VDD_CB VDD_CB VDD_CB VDD_CB P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description Platform Supply Platform Supply Core/L2 Group A Supply Core/L2 Group A Supply Core/L2 Group A Supply Core/L2 Group A Supply Core/L2 Group A Supply ...

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... AJ26 — — — AJ27 — — — AH25 — — — AH26 — — — B19 — DD AF30 I 200Ω 23 (±1 B27 I 200Ω 24 (±1 C21 — internal 9 diode B21 — internal 9 diode Freescale Semiconductor ...

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... NC_K11 NC_K12 NC_K13 NC_K14 NC_R28 NC_T28 NC_U28 NC_V28 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description USB PHY1 Reference Bias Current Generation USB PHY2 Reference Bias Current Generation USB1 PHY 1.8V Output to External Decap USB2 PHY 1 ...

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... AP11 — — 11 AP14 — — 11 AT14 — — 11 A21 — — 41 A25 — — 11 C32 — — 11 D32 — — — — — — — — — — 11 L28 — GND 21 M28 — GND 21 Freescale Semiconductor ...

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... Reserve_P28 Reserve_U32 Reserve_U35 Reserve_AD33 Reserve_AD34 Reserve_AG11 Reserve_AG12 Reserve_AG25 Reserve_AH11 Reserve_AH12 Reserve_AK1 Reserve_AK2 Reserve_AL1 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description — — — — — — — — — — — — ...

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... Pin Assignments and Reset States Signal Reserve_AL2 Reserve_AT19 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev Table 1. Pins Listed by Bus (continued) Signal Description — — Package Pin Power Notes Pin Number Type Supply AL2 — — 11 AT19 — — 41 Freescale Semiconductor ...

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... DD 32. The cfg_xvdd_sel(LAD[26]) reset configuration pin must select the correct voltage that is being supplied on the XV Incorrect voltage select settings can lead to irreversible device damage. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 1. Pins Listed by Bus (continued) Signal Description DD DD ...

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... Package Pin Power Pin Number Type Supply Network.” 1 Maximum Value Unit –0.3 to 1.21 V –0 –0.3 to 1.1 V –0.3 to 1.1 V –0.3 to 1.1 V –0 –0 –0 –0.3 to 2.75 –0.3 to 1.98 Freescale Semiconductor Notes Note 10, 11 — — 1 — — ...

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... Ethernet I/O, Ethernet Management Interface 1 (EMI1), 1588, GPIO Ethernet Management Interface 2 (EMI2) USB PHY Transceiver supply voltage USB PHY PLL supply voltage Low Power Security Monitor Supply P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Electrical Characteristics 1 (continued) Symbol Maximum Value GV – ...

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... IN DD –0.3 to ( –0.3 to ( –0.3 to ( –0.4 to ( _3P3 –0 (USB_V _3P3 + 0.3) DD — –0.3 to (1.2 + 0.3) –55 to 150 stg Freescale Semiconductor Note °C — Figure ...

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... Pad power supply for SerDes transmitter Ethernet I/O, Ethernet Management Interface 1 (EMI1),1588, GPIO supply USB PHY Transceiver supply voltage USB PHY PLL supply voltage Low Power Security Monitor Supply P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Electrical Characteristics Recommended Symbol Value V 1.0 ± 50mV(core ...

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... 105 (max -40 (min 105 (max 0(min (max must be tied to GND, subject to the power DD Freescale Semiconductor Note V — V — V — V — V — V — V — V — °C — °C — °C 3 ...

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... The DDR SDRAM interface uses differential receivers referenced by the externally supplied MV (nominally set appropriate for the SSTL_1.5 electrical signaling standard. The DDR DQS receivers cannot be DD operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor + 20 GND GND – ...

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... 105 °C and at GV (min GND. DD _1P0 DD_PL Table 17. = 1.5 V after a required minimum DD = GND before the system is DD Freescale Semiconductor — — — — — and ...

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... To guarantee MCKE low during power up, the above sequencing for GV DDR signals being in an indeterminate state during power up, the sequencing for GV Incorrect voltage select settings can lead to irreversible device damage. See “Supply Power Default P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor WARNING Fuse programming 10% POV DD ...

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... Freescale Semiconductor = GND before SV DD_CB DD Power Note (W) (W) — — — — — — — — ...

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... Maximum Typical Thermal 1800 700 1300 Maximum Typical Thermal 1600 600 1200 Maximum P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 6. P5020 Power Dissipation (continued) PME/ Junction DD_PL, DD_CA, Freq SV V Temp DD DD_CB, (MHz) (V) (V) (° ...

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... W 0.119 0.134 0.202 0.226 0.367 0.411 0.088 0.099 W 0.139 0.156 0.241 0.270 0.447 0.501 0.075 0.100 W 0.004 0.005 W 0.048 0.120 W Freescale Semiconductor Power Note (W) — — Notes 1,2,5 1,3,6 1,3,6 1,3,6 ...

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... This table shows the estimated power dissipation on the AV voltage levels DD_DDR AV DD_CC1 AV DD_CC2 AV DD_PLAT P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor BVdd (2.5V) BVdd (3.3V) BVdd (1.8V) BVdd (2.5V) BVdd (3.3V) — OVdd (3.3V) — CVdd (1.8V) CVdd (2.5V) CVdd (3.3V) — USB_V _3P3 DD — ...

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... Single-layer board (1s) Four-layer board (2s2p Unit Note mW 1 Unit Note battery when P5020/P5010 is powered down. 6 Symbol Value Unit ° C/W ΘJA ° C/W ΘJA ° C/W ΘJMA ° C/W ΘJMA Freescale Semiconductor Note ...

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... V values are based on the respective min and max The symbol this case, represents the OV IN Conditions.” P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Board — — — Information,” for additional details. Table 3. Symbol ...

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... AC Table 3. Min — — Table 14. CAUTION Typ Max Unit — 166 MHz — — — 4 V/ns — 150 ps — 500 KHz — — V Table 15 are observed. Max Unit Note 60 kHz 1 Freescale Semiconductor Note — 4 — — 2 ...

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... This section describes the AC electrical specifications for the RESET initialization timing requirements. This table provides the RESET initialization AC timing specifications. Table 17. RESET Initialization Timing Specifications Parameter Required assertion time of PORESET Required input assertion time of HRESET P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Min t — G125 t — ...

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... Table 19. Power Supply Ramp Rate Parameter / supplies, MVREF and all AV supplies.) DD Table 3). 1 Min Max Unit 4 — SYSCLKs 2 — SYSCLKs — 5 SYSCLKs Section 2.2, Unit Note μs Min Max Unit — 36000 V/s (typ) voltage is 1.35 V when DD Freescale Semiconductor Note — Note 1, 2 ...

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... This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L SDRAM. Table 21. DDR3L SDRAM Interface DC Electrical Characteristics (GV For recommended operating conditions, see Parameter I/O reference voltage Input high voltage Input low voltage P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min 0.49 × REF ...

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... V should track variations in the REF TT Table 23. . Max Unit — 0 ° /2, A OUT ° OUT Max Unit μA 1250 μA 1250 Freescale Semiconductor Note Note /2, DD Note — — ...

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... Parameter Controller Skew for MDQS—MDQ/MECC 1333 MT/s data rate 1200 MT/s data rate 1066 MT/s data rate 800 MT/s data rate Tolerated Skew for MDQS—MDQ/MECC 1333 MT/s data rate P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min V — ILAC V MVREFn + 0.150 IHAC MVREFn + 0 ...

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... T is the clock period and abs(t DISKEW CISKEW t MCK DISKEW t DISKEW Table 3. 1 Symbol Min t 1.5 MCK Max Unit 275 ps 300 425 .This can be DISKEW CISKEW t DISKEW Max Unit 2.5 ns Freescale Semiconductor Note the Note 2 ...

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... MT/s data rate 800 MT/s data rate MDQ/MECC/MDM output setup with respect to MDQS 1333 MT/s data rate 1200 MT/s data rate 1066 MT/s data rate 800 MT/s data rate P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. 1 Symbol Min t DDKHAS 0.606 0.675 ...

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... DDR timing (DD) for the time t DDKLDX NOTE Table Max Unit ps — — — — — ns 0.6 × MCK memory clock reference MCK describes the DDR timing DDKHMH can be modified through DDKHMH 27 assumed that the clock Freescale Semiconductor Note 5 — — for ...

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... This figure shows the DDR3 and DDR3L SDRAM output timing diagram. MCK MCK ADDR/CMD Write A0 t DDKHMP MDQS[n] MDQ[x] Figure 12. DDR3 and DDR3L Output Timing Diagram P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor tMCK t DDKHMH(max) t DDKHMH(min) Figure 11. t Timing Diagram DDKHMH t MCK ...

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... OH V — OL symbol referenced in IN Table 3. Symbol Min 3 1 Max Unit — V 0.8 V μA ±40 — V 0.4 V values found in Table 3. IN Section 2.1.2, “Recommended Operating = 2 2 Max Unit 1.7 — V — 0.7 V Freescale Semiconductor Note — — Note 1 1 ...

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... For recommended operating conditions, see Parameter SPI_MOSI output—Master data (internal clock) hold time SPI_MOSI output—Master data (internal clock) delay SPI_CS outputs—Master data (internal clock) hold time P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min ) ...

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... Figure 14. eSPI AC Test Load Table 31 in master mode (internal clock). Note that although timing specifications t NIIXKH t NIIVKH t NIKHOV t NIKHOV2 Min Max Unit Note — 6.0 5 — 0 — symbolizes the NMSI NIKHOV Ω NIKHOX t NIKHOX2 Freescale Semiconductor — ns — for ...

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... IEEE Std 1588 interface. 2.12.1 SGMII Timing Specifications Refer to Section 2.20.9, “SGMII Interface.” 2.12.2 MII and RGMII Timing Specifications This section discusses the electrical characteristics for the MII and RGMII interfaces. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol ...

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... V supply 2 Min Max Unit 1.7 — V — 0.7 V μA — ±40 2.0 — V — 0.4 V values found in Table 3. IN Table 2 and Table 3. Min Typ Max 399.96 400 400.04 39.996 40 40.004 Freescale Semiconductor Note 1 — — — Note — — Unit ns ns ...

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... RX_CLK clock rise (20%-80%) RX_CLK clock fall time (80%-20%) Note: The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm. This figure provides the AC test load for eTSEC. Output P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol t t MTXH/ ...

Page 84

... Symbol Min t –500 SKRGT_TX t 1.0 SKRGT_RX t 7.2 RGT RGTH RGT RGTH RGT t — RGTR t — RGTF t MRXR t MRDXKL Typ Max Unit 0 500 ps — 2.6 ns 8.0 8 — — 0.75 ns — 0. the lowest speed RGT Freescale Semiconductor Note — — ...

Page 85

... Ethernet management interface is provided in this table. Table 39. Ethernet Management Interface 1 DC Electrical Characteristics (LV For recommended operating conditions, see Parameter Input high voltage Input low voltage Input high current (LV = Max 2 P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min V 2 — — ...

Page 86

... V — 0.7 V μA — ±40 2.4 — V — 0.4 V values found in Table 3. IN Section 2.1.2, “Recommended Operating Conditions.” Min Max Unit 0.84 — V — 0.36 V — 0 — mA — Freescale Semiconductor Note 1 — — Note — — Note — — — — — ...

Page 87

... Ethernet Management Interface 2 AC Electrical Characteristics Table 43. Ethernet Management Interface 2 AC Timing Specifications For recommended operating conditions, see Parameter/Condition MDC frequency MDC clock pulse width high P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. 1 Symbol Min Typ f — ...

Page 88

... Typ Max Unit — (0.5 ×(1 MDC — — ns — — ns symbolizes MDKHDX . The delay is equal to 0.5 management data MDC t MDCR Typ Max Unit × 7 — RX_CLK — 250 ps — 2.0 ns Freescale Semiconductor Note 3 — — for Note — — ...

Page 89

... Figure 21. eTSEC IEEE 1588 Output AC Timing This figure shows the data and command input AC timing diagram. TSEC_1588_CLK TSEC_1588_TRIG_IN Figure 22. eTSEC IEEE 1588 Input AC Timing P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min t 1.0 T1588CLKINF 2 × ...

Page 90

... Max Unit 2.0 — V — 0.8 V μA — ±40 2.8 — V — 0.3 V _3P3 values found in Table IN Section 2.1.2, “Recommended Symbol Min Typ Max — 24 — t –0.005 0 0.005 CLK_TOL CLK_DUTY t — — 5 CLK_PJ Ω L Freescale Semiconductor Note — 3. Unit MHz % % ps ...

Page 91

... This table provides the DC electrical characteristics for the enhanced local bus interface operating at BV Table 49. Enhanced Local Bus DC Electrical Characteristics (BV For recommended operating conditions, see Parameter Input high voltage Input low voltage P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Characteristics Table 3. Symbol Min V 2 ...

Page 92

... LBKSKEW t 6 LBIVKH t 1 LBIXKH = 1.8 V) (continued) DD Max Unit μA ±40 — V 0.4 V values found in Table 3. IN Section 2.1.2, “Recommended Operating Ω Max Unit — 150 ps — ns — ns Freescale Semiconductor Note 2 — — Note — — 2 — — ...

Page 93

... LBCR[AHD] defaults to 0 and eLBC runs at maximum hold time. 5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK. This figure shows the AC timing diagram of the local bus interface. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. 1 ...

Page 94

... AC timing delay. For example, for GPCM, LCS can be programmed to delay by t (0, ¼, ½ ¼ ½ cycles), so the final delay is t acs P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev LBIVKH t LBKLOV Figure 25. Enhanced Local Bus Signals acs t LBIXKH t LBIVKL t LBIXKL t LBKLOX t LBONOT t LBKLOZ + t . LBKLOV Freescale Semiconductor ...

Page 95

... This table provides the DC electrical characteristics for the eSDHC interface. Table 51. eSDHC Interface DC Electrical Characteristics For recommended operating conditions, see Characteristic Input high voltage Input low voltage Input/output leakage current Output high voltage P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor t addr read data address t LBONOT ...

Page 96

... Table 3. IN and Figure 28. 1 Min Max Unit MHz 0 25/50 20/52 10/7 — ns 10/7 — ns — 2.5 — ns 2.5 — ns – (first three letters of functional block)(signal)(state) for outputs. For example, t Freescale Semiconductor Note — Note FHSKHOV ...

Page 97

... This table provides the DC electrical characteristics for the MPIC interface. Table 53. MPIC DC Electrical Characteristics (OV For recommended operating conditions, see Parameter Input high voltage Input low voltage P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor SHSCK VM = Midpoint Voltage (OV DD ...

Page 98

... V — 0.4 V Table 3. Table 3. Max Unit — SYSCLKs ns to ensure proper operation when PIWID = 3 Max Unit — V — 0.8 V μA — ±40 — V — 0.4 V values found in Table Freescale Semiconductor Note 2 — — Note 1 Note — — ...

Page 99

... All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. This figure provides the AC test load for TDO and the boundary-scan outputs of the device. Output P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Figure 29 Table 56. JTAG AC Timing Specifications Table 3. ...

Page 100

... JTKHKL t JTG VM = Midpoint Voltage ( TRST VM = Midpoint Voltage (OV DD Figure 31. TRST Timing Diagram VM t JTDVKH t JTKLDV VM = Midpoint Voltage (OV DD Figure 32. Boundary-Scan Timing Diagram 2 C interface. t JTGR t JTGF / JTDXKH Input Data Valid Output Data Valid /2) Freescale Semiconductor ...

Page 101

... Data setup time Data input hold time: CBUS compatible masters Data output delay time Setup time for STOP condition Bus free time between a STOP and START condition P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 2 C interfaces Electrical Characteristics (OV Table 3. ...

Page 102

... Min Max Unit 0.1 × OV — 0.2 × OV — — 400 pF symbolizes I I2DVKH clock reference (K) going to I2C IHmin ) of the SCL signal. I2CL Ω I2KHKL t I2PVKH P S Freescale Semiconductor Note — — — timing I2PVKH of the SCL t I2KHDX ...

Page 103

... OH Note: 1. The min V and max V values are based on the respective min and max The symbol this case, represents the LV IN Conditions.” P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol –2 mA) ...

Page 104

... P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 104 Table Ω Figure 35. GPIO AC Test Load Symbol Min Unit PIWID t 3 SYSCLK TIWID to ensure proper operation. PIWID to ensure proper TIWID for the voltage Table Ω L Freescale Semiconductor Note 1 2 ...

Page 105

... The differential waveform is constructed by subtracting the inverting signal (SD_TXn, for example) from the non-inverting signal (SD_TXn, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor or or Differential Swing, V ...

Page 106

... Figure 37. Receiver of SerDes Reference Clocks P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 106 Figure ) ÷ ÷ 2, which is the arithmetic mean of the two = ( SD_TXn SD_TXn ) is 1000 mV p-p. DIFFp-p 50 Ω 50 Ω 41, “Differential Measurement Points for Rise DIFFp Input Amp Freescale Semiconductor ) has 500 mV. ...

Page 107

... Input Amplitude or Differential Peak < 800 mV SD_REF_CLKn SD_REF_CLKn Figure 38. Differential Reference Clock Input DC Requirements (External DC-Coupled) P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ) are as specified in DD Section 2.20.2.1, “SerDes Reference Clock Receiver Figure 38 shows the SerDes reference clock input requirement ...

Page 108

... P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 108 Figure with SD_REF_CLKn either left unconnected or MIN MAX < < SD_REF_CLKn Input Amplitude shows the SerDes reference clock input < Vmax Vcm + 400 mV Vcm > Vmin Vcm – 400 mV Figure 40 shows the SerDes 800 Freescale Semiconductor ...

Page 109

... See Rise Edge Rate V = +200 –200 mV IL – SD_REF_CLKn SD_REF_CLKn Figure 41. Differential Measurement Points for Rise and Fall Time P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min t — CLK_REF t –350 CLK_TOL t 40 CLK_DUTY t — ...

Page 110

... Section 2.20.8, “Serial ATA (SATA) • Section 2.20.9, “SGMII Interface” Note that external AC-coupling capacitor is required for the above serial transmission protocols per the protocol’s standard requirements. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 110 SD_RXn SD_TXn SD_TXn SD_RXn 50 Ω Receiver 50 Ω Freescale Semiconductor ...

Page 111

... DC differential Tx Z TX-DIFF-DC impedance Transmitter DC impedance Z TX-DC Note: 1. Measured at the package pins with a test load of 50Ω to GND on each pin. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Section 2.20.2, “SerDes Reference Clocks.” ( Table 3. Min Typical Max ...

Page 112

... Required well as D– DC impedance during all states = 1 1 Max Unit Note = 2 × |V 1200 mV V RX-DIFFp-p RX-D+ See Note 1. Ω 120 Rx DC differential mode impedance. See Note 2 Freescale Semiconductor | See Note 1. | See Note 1. of the TX-DIFFp-p of the TX-DIFFp-p – RX-D- ...

Page 113

... This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are specified at the component pins. Table 66. PCI Express 2.0 (5 GT/s) Differential Receiver (Rx) Input DC Specifications (SV For recommended operating conditions, see Parameter Differential input peak-to-peak voltage DC differential input impedance P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor (continued) Min Typ 40 50 RX- — ...

Page 114

... Required well as D– DC Impedance (50 ±20% tolerance). See Notes 1 and 2. — kΩ Required well as D– DC Impedance when the Receiver terminations do not have power. See Note 3. 175 RX-IDLE-DET-DIFFp-p 2 × |V – RX-D+ RX-D– Measured at the package pins of the receiver Freescale Semiconductor ...

Page 115

... Tx jitter budget collected over any 250 consecutive Tx UIs. Note that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. The chip’s SerDes transmitter does not have C P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Min Typ ...

Page 116

... All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 4. TX-EYE-MEDIAN-to-MAX-JITTER built-in. An external AC coupling capacitor is required. TX Note = 1 – 0.25 UI. TX-EYE Figure 44 and measured over any 250 = 0.25 UI for the TX-JITTER-MAX median is less than half of the total Freescale Semiconductor ...

Page 117

... It is recommended that the recovered calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. ...

Page 118

... See Note 1. 0.4 UI The maximum inherent total timing error for common RefClk Rx architecture 0.34 UI Max Rx inherent total timing error 0.30 UI The maximum inherent deterministic timing error for common RefClk Rx architecture 0.24 UI The maximum inherent deterministic timing error for common RefClk Rx architecture Figure 44 Ω Freescale Semiconductor ...

Page 119

... TD and TD is 500 mV p-p. The differential output signal ranges between 500 mV and –500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor , is defined as V – V ...

Page 120

... Voltage relative to COMMON of either signal comprising a differential pair. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 120 Section 2.20.2, “SerDes Reference Clocks.” Table 3. Symbol Min V –0. 800 DIFFPP V 500 DIFFPP = 1 1 Typ Max Unit — 2.30 V — 1600 mV p-p — 1000 mV p-p Freescale Semiconductor Note 1 — — ...

Page 121

... Table 74. sRIO Receiver AC Timing Specifications For recommended operating conditions, see Parameter Deterministic jitter tolerance Combined deterministic and random jitter tolerance 2 Total jitter tolerance Bit error rate P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min V 200 IN Table 3. Symbol ...

Page 122

... P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 122 Table 3. Symbol Min Typical UI 400 – 100ppm UI 320 – 100ppm UI 200 – 100ppm Frequency Max Unit 400 400 + 100ppm ps 320 320 + 100ppm ps 200 200 + 100ppm ps Figure 46. The sinusoidal jitter component 1.875 MHz 20 MHz Freescale Semiconductor Note — — — ...

Page 123

... Measured at the receiver. 2.20.6.2 XAUI AC Timing Specifications This section discusses the XAUI AC timing specifications for the clocking signals, transmitter, and receiver. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Section 2.20.2.2, “DC Level Requirement for SerDes Reference Clocks.” Table 3. Symbol Min ...

Page 124

... V/ns 200 — — mV — — –200 mV — — Max Unit 0.17 UI p-p 0.35 UI p-p 320 + 100 ppm ps Freescale Semiconductor Note — — — — — Note — — — ...

Page 125

... For more information on these specifications, see 2.20.7.1.2 Aurora Transmitter DC Electrical Characteristics This table defines the Aurora transmitter DC electrical characteristics. Table 80. Aurora Transmitter DC Electrical Characteristics (XV For recommended operating conditions, see Parameter Differential output voltage P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min Typical J 0.37 — ...

Page 126

... T UI 400 – 100 ppm UI 320 – 100 ppm UI 200 – 100 ppm = 1 1 Max Unit Note 1200 mV p-p or Section 2.20.8.2.1, “AC Typical Max Unit — 0.17 UI p-p — 0.35 UI p-p 400 400 + 100 ppm ps 320 320 + 100 ppm ps 200 200 + 100 ppm ps Freescale Semiconductor 1 ...

Page 127

... This table provides the DC differential transmitter output DC characteristics for the transmission. Table 84. Gen1i/1.5G Transmitter (Tx) DC Specifications (XV For recommended operating conditions, see Parameter Tx differential output voltage Tx differential pair impedance Note: 1. Terminated by 50 Ω load impedance P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min Typical J 0. ...

Page 128

... Typ Max Unit — 700 mV p-p Ω 100 115 = 1 1 Typical Max Unit — 600 mV p-p Ω 100 115 120 240 mV p Typical Max Unit — 750 mV p-p Ω 100 115 120 240 mV p-p Freescale Semiconductor Note 1 — Note Note ...

Page 129

... In a frequency band from 150 kHz to 15 MHz at BER Total peak-to-peak deterministic jitter should be less than or equal to 50 ps. This figure shows the reference clock timing waveform. Ref_CLK Figure 47. Reference Clock Timing Waveform P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol t CLK_REF ...

Page 130

... SATA_TXDJfB/500 U — SATA_TXDJfB/1667 Typ Max Unit 1.5 — Gbps 666.6667 670.2333 ps — 0.355 UI p-p — 0.47 UI p-p — 0.175 UI p-p — 0.22 UI p-p Typ Max Unit 3.0 — Gbps 333.3333 335.1167 ps — 0.3 UI p-p — 0.37 UI p-p — 0.55 UI p-p — 0.17 UI p-p — 0.19 UI p-p — 0.35 UI p-p Freescale Semiconductor Note — — Note — — ...

Page 131

... When operating in SGMII mode, the EC_GTX_CLK125 clock is not required for this port. Instead, a SerDes reference clock is required on SD_REF_CLK[1:3] and SD_REF_CLK[1:3] pins. SerDes banks 1-3 may be used for SerDes SGMII configurations based on the RCW Configuration field SRDS_PRTCL. For more information on these specifications, see P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min T 666 ...

Page 132

... Max Unit Note 1 -max — 725.0 mV B(1-3)TECR(lane)0[A MP_RED] =0b000000 665.6 B(1-3)TECR(lane)0[A MP_RED] =0b000010 604.7 B(1-3)TECR(lane)0[A MP_RED] =0b000101 545.2 B(1-3)TECR(lane)0[A MP_RED] =0b001000 482.9 B(1-3)TECR(lane)0[A MP_RED] =0b001100 423.4 B(1-3)TECR(lane)0[A MP_RED] =0b001111 362.5 B(1-3)TECR(lane)0[A MP_RED] =0b010011 Ω 60 — = 2*|V | TX-DIFFp Freescale Semiconductor ...

Page 133

... Receiver Figure 48. 4-Wire AC-Coupled SGMII Serial Link Connection Example This figure shows the SGMII transmitter DC measurement circuit. SGMII SerDes Interface Transmitter Figure 49. SGMII Transmitter DC Measurement Circuit P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor SD_TXn 50 Ω SD_RXn Ω ...

Page 134

... Unit Max 2.30 V 1600 mV p Typ Max Unit N/A — — 1200 mV — 30 — 100 mV 65 — 175 Ω 80 — 120 Section 2.20.4.5.2, “PCI Express Max Unit 1600 mV p-p Freescale Semiconductor Note 1 — Note — Note 1 ...

Page 135

... Source synchronous clocking is not supported. Clock is recovered from the data. Table 98. SGMII Receive AC Timing Specifications For recommended operating conditions, see Parameter Deterministic jitter tolerance Combined deterministic and random jitter tolerance Total jitter tolerance P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 3. Symbol Min Typ JD — ...

Page 136

... Section 3.1.3, “e5500-64 Core Complex to SYSCLK Section 3.1.5, “DDR Controller PLL Ratios.” Typ Max Unit Note -12 — 10 — 800 800 + 100 ppm ps 320 320 + 100 ppm ps Figure 46. The sinusoidal jitter component Figure Table Freescale Semiconductor — 46. 102. ...

Page 137

... For the FMan: 300 MHz is the minimum to support 1 G. 450 MHz is the minimum to support 10 G. 500 MHz is the minimum to support 10 G with PCD. 600 MHz is the minimum to support 2*1 G) with PCD. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Maximum Processor Core Frequency 1600 MHz ...

Page 138

... P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 138 Table 100. Platform to SYSCLK PLL Ratios Binary Value of Platform:SYSCLK Ratio SYS_PLL_RAT 0_0100 4:1 0_0101 5:1 0_0110 6:1 0_0111 7:1 0_1000 8:1 All Others Reserved Core Complex:SYSCLK 0_1000 0_1001 0_1010 0_1011 0_1100 0_1110 0_1111 1_0000 1_0001 1_0010 All Others Ratio 8:1 9:1 10:1 11:1 12:1 14:1 15:1 16:1 17:1 18:1 Reserved Freescale Semiconductor ...

Page 139

... The RCW Configuration field DDR_RATE (bit 232) must be set to b’0 for asynchronous mode, and b’1 for synchronous mode. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 102. Core Complex [0,1] PLL Select e5500 Core Complex 0 Clock CC1 PLL /1 ...

Page 140

... Table 103. Asynchronous DDR Clock Ratio DDR:SYSCLK Ratio 5:1 6:1 8:1 9:1 10:1 12:1 13:1 Reserved Table 104. Synchronous DDR Clock Ratio DDR:Platform CLK Ratio Set MEM_PLL_CFG=01 for Platform CLK Freq 1:1 Reserved Set MEM_PLL_CFG = 01 for SYSCLK Freq >96.7 MHz >80.6 MHz >120.9 MHz >107.4 MHz >96.7 MHz >80.6 MHz >74.4 MHz — >600 MHz — Freescale Semiconductor 1 1 ...

Page 141

... Figure 53. Serial RapidIO Minimum Platform Frequency See Section 19.4, “LP-Serial Signal Descriptions,” in the reference manual for your chip for Serial RapidIO interface width and frequency details. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor SYSCLK (MHz) 125 133.3 Platform Frequency (MHz) ...

Page 142

... Table 107. SerDes Bank 1 PLL Dividers SerDes Bank 1 PLL Divider Divide by 1 off Bank 1 PLL Divide by 2 off Bank 1 PLL Table 108 (Bank 3) 20:1 25:1 40:1 50:1 24:1 30:1 Reserved SerDes Bank n PLL Divider Divide by 1 off Bank n PLL Divide by 2 off Bank n PLL Freescale Semiconductor ...

Page 143

... I/Os associated with the BVDD, CVDD, and LVDD power planes, respectively. Incorrect voltage select settings can lead to irreversible device damage. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Table 109. Frame Manager Clock Select FM Frequency 0b0 ...

Page 144

... VDD Voltage Selection CVDD 3.3 V 3.3 V 2.5 V 2.5 V 1.8 V 1.8 V 3.3 V 3.3 V 2.5 V 2.5 V 1.8 V 1.8 V 3.3 V 3.3 V 2.5 V 2.5 V 1.8 V 1.8 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Reserved and AV voltages must be derived DD_CCn DD_DDR voltages must be derived directly from DD_SRDSn Freescale Semiconductor LVDD 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V ...

Page 145

... sourced from voltage source (for example when using DDR3 1.8 V), is illustrated in DD P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor pin being supplied to minimize noise coupled from nearby circuits. DD pin, which is on the periphery of the footprint, without DD NOTE ...

Page 146

... An example solution for USB_V DD_PL , is illustrated in Figure DD_PL Bulk and Decoupling Capacitors C1 GND _1P0 Power Supply Filter Circuit DD 1 1.8V source DD 57. The component values in this example filter F1 V DD_PL Freescale Semiconductor _1P0 , and ...

Page 147

... Low Power features are not used. Otherwise the LP_Section will generate internal errors, which will prevent the high power trust section from reaching Trusted/Secure state. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor DD as required. All unused active high inputs should be connected to GND. All and GND pins of the device ...

Page 148

... No pull-up/pull-down is required for TDI, TMS, or TDO. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 148 allows the COP port to independently assert PORESET or TRST, while ensuring that the is common to all known emulators. Figure Figure 58, for connection to the target Figure 59. If this is not possible, the Freescale Semiconductor 59. ...

Page 149

... COP_SRESET COP_HRESET COP_CHKSTP_OUT Figure 58. Legacy COP Connector Physical Pinout P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor COP_TDO COP_TDI 3 4 COP_TRST COP_VDD_SENSE COP_TCK 7 8 COP_CHKSTP_IN COP_TMS KEY 13 No pin GND 15 16 Hardware Design Considerations ...

Page 150

... A 5 COP_TRST 10 Ω 2 COP_VDD_SENSE NC COP_CHKSTP_OUT 10 kΩ COP_CHKSTP_IN System logic COP_TMS COP_TDO COP_TDI COP_TCK kΩ 6 HRESET 1 10 kΩ PORESET 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 TRST CKSTP_OUT 10 kΩ TMS TDO TDI TCK P5020/P5010 Freescale Semiconductor ...

Page 151

... If the Aurora interface is not used, Freescale recommends the legacy COP header be designed into the system as described in Section 3.6.1.1, “Termination of Unused Figure 60. Aurora 22 Pin Connector Duplex Pinout P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Figure 63. Signals.” 1 ...

Page 152

... GND GND RX2+ N RX2 GND GND N/C 43 RX3 RX3- N/C GND 47 48 GND N/C TX4 TX4- N GND 53 54 GND TX5+ N N/C 57 TX5- GND GND TX6+ N N/C TX6- GND 65 GND N/C TX7+ 69 N/C TX7- 70 Freescale Semiconductor ...

Page 153

... TRST line. If BSDL testing is not being performed, this switch must be closed to position B. 4. Asserting HRESET causes a hard reset on the device. HRESET is not used by the Aurora 22 pin connector. Figure 62. Aurora 22 Pin Connector Duplex Interface Connection P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor RESET ...

Page 154

... RX0_P RX0_N RX1_P RX1_N kΩ 4 HRESET 1 10 kΩ PORESET 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 TRST TMS TDO TDI TCK Ω EVT[4] EVT[4] EVT[1] EVT[0] SD_TX09_P SD_TX09_N SD_TX08_P SD_TX08_N SD_RX09_P SD_RX09_N SD_RX08_P SD_RX08_N P5020 Freescale Semiconductor ...

Page 155

... USB Controller Connections This section details the hardware connections required for the USB controllers. P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor Hardware Design Considerations 1 for the unused banks to power down the SerDes bank = 155 ...

Page 156

... F(Max) VBUS Charge Pump 0 Figure 64. Divider Network at VBUS Value 1 μ 1.5 μ μ μ μ 0.8 V. USBn_DRVVBUS USBn_PWRFAULT USBn_VBUS_CLMP P5020 _1P8_DECAP DD ESR Package 2 Ω B(3528) 1.5 Ω Low ESR 0603 200 m-Ω 0603 1.5 Ω B(3528) Freescale Semiconductor — ...

Page 157

... The die junction-to-case thermal resistance • The die junction-to-lid-top thermal resistance • The die junction-to-board thermal resistance P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor FC-PBGA Package (Small Lid) Heat Sink Heat Sink Clip Hardware Design Considerations ...

Page 158

... The package parameters are as provided in the following list. The package type is 37.5 mm × 37.5 mm, 1295 flip chip plastic ball grid array (FC-PBGA). P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 158 Radiation Convection Heat Sink Junction to lid top Radiation Convection Figure 65). Junction to case top Thermal Interface Material Die/Package Die Junction Package/Solder balls Freescale Semiconductor ...

Page 159

... Mechanical Dimensions of the FC-PBGA This figure shows the mechanical dimensions and bottom surface nomenclature of the chip. Figure 67. Mechanical Dimensions of the FC-PBGA with Full Lid Notes: P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 37.5 mm × 37.5 mm 1295 1.0 mm 0.60 mm 96.5% Sn, 3% Ag, 0. 3.53 mm (Maximum) ...

Page 160

... Section 2.2, “Power Up Sequencing.” POV are shown Package CPU Encryption Type Speed 1200 MHz FC-PBGA Q = 1600 MHz Present Pb free T = 1800 MHz V = 2000 MHz Freescale Semiconductor DD Figure DDR Die Data rate Revision M = 1200 A = Rev N = 1333 1 Rev 2.0 ...

Page 161

... Representative for more information on orderable parts as not all combinations of orderable part numbers are available. Table 113. Orderable Part Numbers Addressed by This Document Part Number p n P5020NSE1MMB cores P5020NSN1MMB P5020NSE1QMB P5020NSN1QMB P5020NSE1TNB P5020NSN1TNB P5020NSE1VNB P5020NSN1VNB P5020NXE1QMB P5020NXN1QMB P5020NXE1TNB P5020NXN1TNB P5010NSE1MMB cores P5010NSN1MMB P5010NSE1QMB P5010NSN1QMB P5010NSE1TNB ...

Page 162

... Revision History 7 Revision History This table provides a revision history for this document. Revision Date 0 03/2013 • Initial public release P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0 162 Table 114. Revision History Description Freescale Semiconductor ...

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... Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. " ...