P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet - Page 109

• Manufacturer Part Number: P5020NSE1VNB
• Description: Processors - Application Specialized Std Tmp Enc2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSE1VNB

• Rohs: yes

2.20.2.3
This table lists AC requirements for the PCI Express, SGMII, Serial RapidIO and Aurora SerDes reference clocks to be
guaranteed by the customer’s application design.
Freescale Semiconductor
For recommended operating conditions, see
SD_REF_CLK/SD_REF_CLK frequency range
SD_REF_CLK/SD_REF_CLK clock frequency
tolerance
SD_REF_CLK/SD_REF_CLK reference clock duty
cycle
SD_REF_CLK/SD_REF_CLK max deterministic
peak-peak jitter at 10
SD_REF_CLK/SD_REF_CLK total reference clock
jitter at 10
SD_REF_CLK/SD_REF_CLK rising/falling edge rate
Differential input high voltage
Differential input low voltage
Rising edge rate (SD_REF_CLKn) to falling edge rate
(SD_REF_CLKn) matching
Note:
1. Caution: Only 100 and 125 have been tested. In-between values not work correctly with the rest of the system.
2. Limits from PCI Express CEM Rev 2.0
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn).
4. Measurement taken from differential waveform
5. Measurement taken from single-ended waveform
6. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
V
V
SD_REF_CLKn
SD_REF_CLKn
The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate
of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See
IH
IL
= –200 mV
= +200 mV
-6
Table 62. SD_REF_CLKn and SD_REF_CLKn Input Clock Requirements (SV
BER (peak-to-peak jitter at refClk input)
0.0 V
AC Requirements for SerDes Reference Clocks
–
Parameter
-6
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
BER
Figure 41. Differential Measurement Points for Rise and Fall Time
Rise Edge Rate
Table
3.
Figure
Figure
42.
t
CLKRR/
t
41.
Matching
t
CLK_DUTY
Rise-Fall
t
Symbol
CLK_REF
CLK_TOL
t
t
CLK_DJ
CLK_TJ
V
V
IH
IL
t
CLKFR
–350
Min
200
—
40
—
—
—
—
1
100/125
Fall Edge Rate
Typ
—
—
—
—
—
—
—
50
–200
Max
350
42
86
20
—
—
60
4
Electrical Characteristics
DD
= 1.0 V)
MHz
V/ns
Unit
ppm
mV
mV
ps
ps
%
%
Note
5,
—
—
1
4
2
3
4
4
6
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