P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet - Page 123
P5020NSE1VNB
Manufacturer Part Number
P5020NSE1VNB
Description
Processors - Application Specialized Std Tmp Enc2000/1333
Manufacturer
Freescale Semiconductor
Datasheet
1.P5010NXN1QMB.pdf
(163 pages)
Specifications of P5020NSE1VNB
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2.20.6.1.1
Only SerDes banks 2–3 (SD_REF_CLK[2:3] and SD_REF_CLK[2:3]) may be used for various SerDes XAUI configurations
based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1.
For more information on these specifications, see
2.20.6.1.2
This table defines the XAUI transmitter DC electrical characteristics.
2.20.6.1.3
This table defines the XAUI receiver DC electrical characteristics.
2.20.6.2
This section discusses the XAUI AC timing specifications for the clocking signals, transmitter, and receiver.
Freescale Semiconductor
For recommended operating conditions, see
For recommended operating conditions, see
Output voltage
Differential output voltage
Note:
Differential input voltage
Note:
1. Absolute output voltage limit
1. Measured at the receiver.
Parameter
Parameter
XAUI AC Timing Specifications
Table 75. XAUI Transmitter DC Electrical Characteristics (XV
DC Requirements for XAUI SD_REF_CLKn and SD_REF_CLKn
XAUI Transmitter DC Electrical Characteristics
XAUI Receiver DC Electrical Characteristics
Table 76. XAUI Receiver DC Timing Specifications (SV
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Symbol
V
Table
Table
DIFFPP
V
Symbol
O
3.
3.
V
IN
Section 2.20.2.2, “DC Level Requirement for SerDes Reference Clocks.”
–0.40
Min
800
Min
200
Typical
Typical
900
—
—
DD
DD
= 1.5 V or 1.8 V)
1600
Max
= 1.5 V or 1.8 V)
1600
Max
2.30
Electrical Characteristics
mV p-p
Unit
mV p-p
Unit
V
Note
1
Note
—
1
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