P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet - Page 69

• Manufacturer Part Number: P5020NSE1VNB
• Description: Processors - Application Specialized Std Tmp Enc2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSE1VNB

• Rohs: yes

EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK125 rise and fall time
EC_GTX_CLK125 duty cycle
EC_GTX_CLK125 jitter
Note:
1. Rise and fall times for EC_GTX_CLK125 are measured from 20% to 80% (rise time) and 80% to 20% (fall time) of LV
2. EC_GTX_CLK125 is used to generate the GTX clock for the dTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty
2.6.3
The real time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an
input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum pulse
width of the RTC signal should be greater than 16× the period of the platform clock with a 50% duty cycle. There is no minimum
RTC frequency; RTC may be grounded if not needed.
2.6.4
This table provides the dTSEC gigabit Ethernet reference clocks AC timing specifications.
2.6.5
A description of the overall clocking of this device is available in the reference manual for your chip in the form of a clock
subsystem block diagram. For information on the input clock requirements of functional blocks sourced external of the device,
such as SerDes, Ethernet Management, eSDHC, Local Bus, see the specific interface section.
2.7
This section describes the AC electrical specifications for the RESET initialization timing requirements. This table provides the
RESET initialization AC timing specifications.
Freescale Semiconductor
Required assertion time of PORESET
Required input assertion time of HRESET
cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the dTSEC GTX_CLK.
See
Section 2.12.2.3, “RGMII AC Timing Specifications,”
Parameter/Condition
RESET Initialization
Real Time Clock Timing
dTSEC Gigabit Ethernet Reference Clock Timing
Other Input Clocks
1000Base-T for RGMII
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Parameter
LV
LV
Table 16. EC_GTX_CLK125 AC Timing Specifications
Table 17. RESET Initialization Timing Specifications
DD
DD
= 2.5 V
= 3.3 V
t
t
G125R
G125H
Symbol
t
t
G125
G125
—
/t
/t
G125F
G125
for duty cycle for 10Base-T and 100Base-T reference clock.
Min
47
—
—
—
—
Min
32
1
Typical
125
—
—
—
8
Max
—
—
± 150
Max
0.75
1.0
53
—
—
Electrical Characteristics
SYSCLKs
Unit
ms
1
Unit
MHz
ns
ns
ps
%
Note
1,
DD
3
.
2
Note
—
—
1
2
2
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