P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet - Page 56

• Manufacturer Part Number: P5020NSE1VNB
• Description: Processors - Application Specialized Std Tmp Enc2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSE1VNB

• Rohs: yes

Electrical Characteristics
Input voltage
Storage junction temperature range
Note:
56
1. Functional operating conditions are given in
2. Caution: MV
3. Caution: LV
4. Caution: CV
5. Caution: BV
6. Caution: OV
7. (C,S,B,G,L,O)V
8. Ethernet Management Interface 2 pins function as open drain I/Os. The interface should conform to 1.2 V nominal voltage
9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
10.Implementation may choose either V
11.V
at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage
to the device.
power-on reset and power-down sequences.
power-on reset and power-down sequences.
power-on reset and power-down sequences.
power-on reset and power-down sequences.
power-on reset and power-down sequences.
levels. LV
sense pin.
regulator, it is recommended that V
DD_PL
voltage must not exceed V
7
DD
IN
must be powered to use this interface.
IN
IN
IN
IN
must not exceed LV
must not exceed BV
must not exceed CV
must not exceed OV
IN
must not exceed GV
DDR3 and DDR3L DRAM signals
DDR3 and DDR3L DRAM reference
Ethernet signals (except EMI2)
eSPI, eSHDC signals
Enhanced Local Bus signals
DUART, I
control and power management, clocking,
debug, I/O voltage select, and JTAG I/O
signals
SerDes signals
USB PHY Transceiver signals
Ethernet Management Interface 2 (EMI2)
signals
may overshoot (for V
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table 2. Absolute Maximum Operating Conditions
Parameter
2
C, DMA, MPIC, GPIO, system
DD
DD_CA
DD_CA
DD
DD
DD
DD
DD_PLn
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IH
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
) or undershoot (for V
or V
be used.
Table
pin for feedback loop. If the platform and core groups are supplied by a single
DD_CB
3. Absolute maximum ratings are stress ratings only; functional operation
.
IL
) to the voltages and maximum duration shown in
USB_V
Symbol
MV
MV
CV
BV
OV
SV
LV
T
—
REF
stg
IN
IN
IN
IN
IN
IN
IN
_3P3
n
1
(continued)
(USB_V
–0.3 to (GV
–0.3 to (GV
–0.3 to (CV
–0.3 to (OV
–0.3 to (BV
–0.4 to (SV
–0.3 to (LV
–0.3 to (1.2 + 0.3)
Maximum Value
–55 to 150
–0.3 to
DD
_3P3 + 0.3)
DD
DD
DD
DD
DD
DD
DD
Freescale Semiconductor
/2+ 0.3)
+ 0.3)
+ 0.3)
+ 0.3)
+ 0.3)
+ 0.3)
+ 0.3)
Unit
°C
V
V
V
V
V
V
V
V
V
Figure
Note
2,
2,
3,
4,
5,
6,
—
7
7
7
7
7
7
7
7
7
8.