P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet - Page 72

• Manufacturer Part Number: P5020NSE1VNB
• Description: Processors - Application Specialized Std Tmp Enc2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSE1VNB

• Rohs: yes

Electrical Characteristics
This table provides the DDR controller interface capacitance for DDR3 and DDR3L.
For recommended operating conditions, see
This table provides the current draw characteristics for MVREFn.
2.9.2
This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports
DDR3 and DDR3L memories. Note that the required GV
required GV
72
For recommended operating conditions, see
For recommended operating conditions, see
Input/output capacitance: DQ, DQS, DQS
Delta input/output capacitance: DQ, DQS, DQS
Note:
Current draw for DDR3 SDRAM for MVREFn
Current draw for DDR3L SDRAM for MVREFn
I/O leakage current
Output high current (V
Output low current (V
Note:
1. This parameter is sampled. GV
2. This parameter is sampled. GV
1. GV
2. MV
3. V
4. The voltage regulator for MV
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V
7. Refer to the IBIS model for the complete output IV curve characteristics.
8. I
V
V
voltage supply may or may not be from the same source.
noise on MV
equal to MV
DC level of MVREFn.
OH
OUT
OUT
TT
DD
REF
Table 21. DDR3L SDRAM Interface DC Electrical Characteristics (GV
and I
is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
(peak-to-peak) = 0.150 V.
(peak-to-peak) = 0.167 V.
is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s
n is expected to be equal to 0.5 × GV
DD
OL
DDR3 and DDR3L SDRAM Interface AC Timing Specifications
Parameter
(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.
REF
are measured at GV
REF
Parameter
n with a min value of MV
n may not exceed the MV
Parameter
OUT
OUT
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
= 0.641 V)
= 0.641 V)
Table 23. Current Draw Characteristics for MVREFn
REF
Table 22. DDR3 and DDR3L SDRAM Capacitance
DD
DD
n must meet the specifications stated in
DD
= 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, T
= 1.35 V – 0.067 V ÷ + 0.100 V (for DDR3L), f = 1 MHz, T
Table
Table
Table
= 1.283 V
REF
Symbol
3.
3.
3.
REF
I
I
I
OH
OZ
OL
DD
n – 0.04 and a max value of MV
MIVREFn
MIVREFn
n DC level by more than ±1% of the DC value (that is, ±13.5 mV).
Symbol
and to track GV
DD
Symbol
C
C
(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the
DIO
IO
≤
V
OUT
23.3
DD
Min
–50
—
DC variations as measured at the receiver. Peak-to-peak
≤
Min
—
—
GV
Min
DD
—
6
Table
.
REF
A
23.
= 25 °C, V
n + 0.04. V
DD
–23.3
Max
50
—
Max
0.5
1250
1250
Max
8
= 1.35 V)
OUT
TT
A
should track variations in the
= GV
= 25 °C, V
Freescale Semiconductor
DD
1
(continued)
/2,
Unit
pF
pF
Unit
mA
mA
OUT
μA
Unit
μA
μA
= GV
DD
Note
Note
7,
7,
1,
1,
Note
6
/2,
—
—
8
8
2
2