CD4093BCM_Q Fairchild Semiconductor, CD4093BCM_Q Datasheet

CD4093BCM_Q

Manufacturer Part Number

CD4093BCM_Q

Description

Logic Gates Qd 2-Inp NAND Sc Trg

Manufacturer

Fairchild Semiconductor

Datasheet

1.CD4093BCM_Q.pdf (8 pages)

Specifications of CD4093BCM_Q

Product

NAND

Logic Family

CD4K

Number Of Gates

Number Of Lines (input / Output)

2 / 1

High Level Output Current

- 4.2 mA

Low Level Output Current

4.2 mA

Propagation Delay Time

450 ns, 210 ns, 160 ns

Supply Voltage - Max

15 V

Supply Voltage - Min

3 V

Maximum Operating Temperature

+ 125 C

Mounting Style

SMD/SMT

Package / Case

SOIC-14

Minimum Operating Temperature

- 55 C

Number Of Input Lines

Number Of Output Lines

Current page: 1 of 8
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CD4093BCM

CD4093BCN

CD4093BC

Quad 2-Input NAND Schmitt Trigger

General Description

The CD4093B consists of four Schmitt-trigger circuits.

Each circuit functions as a 2-input NAND gate with Schmitt-

trigger action on both inputs. The gate switches at different

points for positive and negative-going signals. The differ-

ence between the positive (V

All outputs have equal source and sink currents and con-

form to standard B-series output drive (see Static Electrical

Characteristics).

Features

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Wide supply voltage range:

Schmitt-trigger on each input

with no external components

Noise immunity greater than 50%

) is defined as hysteresis voltage (V

Package Number

M14A

N14A

) and the negative voltage

3.0V to 15V

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Assignments for SOIC and DIP

DS005982.prf

Top View

Applications

• Wave and pulse shapers

• High-noise-environment systems

• Monostable multivibrators

• Astable multivibrators

• NAND logic

Equal source and sink currents

No limit on input rise and fall time

Standard B-series output drive

Hysteresis voltage (any input) T

Typical

Guaranteed

Package Description

5.0V

10V

15V

October 1987

Revised January 1999

25 C

www.fairchildsemi.com

1.5V

2.2V

2.7V

0.1 V

Related parts for CD4093BCM_Q

CD4093BCM_Q Summary of contents

Page 1

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 1999 Fairchild Semiconductor Corporation Equal source and sink currents No limit on input rise and fall time ...

Page 2

Absolute Maximum Ratings (Note 2) DC Supply Voltage ( Input Voltage ( Storage Temperature Range ( Power Dissipation ( Dual-In-Line Small Outline ) Lead Temperature (T L (Soldering, 10 ...

Page 3

AC Electrical Characteristics pF, R 200k, Input ns, unless otherwise specified Symbol Parameter Propagation Delay Time PHL PLH Transition Time ...

Page 4

Typical Applications Assume then PHL PLH [(V V )/( ...

Page 5

Typical Performance Characteristics Typical Transfer Characteristics Guaranteed Hysteresis Input and Output Characteristics NML IH(MIN) OL IH(MIN) T (MIN NMH OH IL(MAX) DD IL(MAX ...

Page 6

AC Test Circuits and Switching Time Waveforms www.fairchildsemi.com 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...

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