BR24L01AF-WE2 Rohm Semiconductor, BR24L01AF-WE2 Datasheet - Page 13

• Manufacturer Part Number: BR24L01AF-WE2
• Description: IC EEPROM 1KBIT 400KHZ 8SOP
• Manufacturer: Rohm Semiconductor

Specifications of BR24L01AF-WE2

• Memory Size: 1K (128 x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOP
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Memory Configuration: 128 X 8
• Interface Type: I2C, Serial
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: BR24L01AF-WE2TR

●Read Command
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BR24L□□-W Series,BR24S□□□-W Series
www.rohm.com
○Read cycle
SDA
LINE
SDA
LINE
S D A
L IN E
S D A
L IN E
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used
when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address
data can be read in succession.
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at
Note)
Fig.47 Difference of slave address of each type
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
address data can be read in succession.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
SCL signal 'H'.
S
T
A
R
T
Fig.43 Random read cycle (BR24L01A/02/04/08/16-W)
Fig.44 Random read cycle (BR24L32/64 -W)
Fig.45 Current read cycle
Fig.46 Sequential read cycle (in the case of current read cycle)
S
T
A
R
T
S
T
A
R
T
S
A
R
T
T
1 0
1 0
1 0
1 0
ADDRESS
A D D R E S S
SLAVE
1
Note)
A D D R E S S
ADDRESS
Note）
N o te )
S L A V E
1
SLAVE
1
0
S LA V E
1
A2
0
0
N o te)
A 2
A1
A2
0
A0
A 2
A 1
A1
R
W
/
W
1 0
R
T
E
A 0
A0
I
A 1
A
C
K
W
W
A 0
R
A
D
R
W
R
T
E
R
E
/
I
/
*
A
C
K
C
A
K
ADDRESS（ｎ）
W
R
E
A
D
R
* *
/
*1
W A
1st WORD
D7
1
7
C
A
K
WA
12
*1
A D D R E S S (n )
D 7
0
WA
11
DATA(n)
W O R D
*1 *2 *3
A 2
D A TA (n )
A 1
A
C
K
A 0
W A
0
D0
ADDRESS（ｎ）
2nd WORD
A
C
K
C
A
K
D 0
S
T
A
R
T
1 0
A
C
K
A D D R E S S
S
O
P
T
WA
S L A V E
1
0
0
A
C
K
A 2
S
T
A
R
T
A 1
1 0
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
A 0
ADDRESS
SLAVE
1
W
R
E
A
D
R
/
A
C
K
0
A
C
K
D7
A2 A1
D 7
A0
DATA(n+x)
13/40
R
W
/
D
R
E
A
D A TA (n )
A
C
K
D7
DATA(n)
D0
D 0
C
A
K
C
A
K
O
S
T
P
O
S
T
P
D0
A
C
K
O
P
S
T
*1 As for WA7, BR24L01A-W become Don’t care.
*1 As for WA12, BR24L32-W become Don’t care.
It is necessary to input 'H' to
the last ACK.
It is necessary to input 'H' to
the last ACK.
Technical Note
2009.09 - Rev.D