C8051F564-IMR Silicon Labs, C8051F564-IMR Datasheet - Page 171

• Manufacturer Part Number: C8051F564-IMR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB CAN2.0 LIN 2.1 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F564-IMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); and similarly when the UART, CAN or LIN are selected, the Crossbar assigns both pins
associated with the peripheral (TX and RX). UART0 pin assignments are fixed for bootloading purposes:
UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. CAN0 pin assignments are
fixed to P0.6 for CAN_TX and P0.7 for CAN_RX. Standard Port I/Os appear contiguously after the priori-
tized functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
As an example configuration, if CAN0, SPI0 in 4-wire mode, and PCA0 Modules 0, 1, and 2 are enabled on
the crossbar with P0.1, P0.2, and P0.5 skipped, the registers should be set as follows: XBR0 = 0x06
(CAN0 and SPI0 enabled), XBR1 = 0x0C (PCA0 modules 0, 1, and 2 enabled), XBR2 = 0x40 (Crossbar
enabled), and P0SKIP = 0x26 (P0.1, P0.2, and P0.5 skipped). The resulting crossbar would look as shown
in Figure 19.4.
P o rt
S p e cia l
F u n ctio n
S ig n a ls
P IN I/O
UA RT _T X
UA RT _R X
CA N_T X
CA N_R X
S C K
M IS O
M O S I
NS S
S D A
S C L
CP 0
CP 0A
CP 1
CP 1A
S YS CL K
CEX 0
CEX 1
CEX 2
CEX 3
CEX 4
CEX 5
ECI
T 0
T 1
L IN _T X
L IN _RX
0
1
2
3
P 0
Figure 19.3. Peripheral Availability on Port I/O Pins
4
5
6
7
0
1
2
3
P 1
4
Rev. 1.1
5
6
7
0
1
and 32-pin pac k ages
2
available on 40-pin
C8051F55x/56x/57x
P 2.2-P 2.7, P 3.0
3
P 2
4
5
6
7
0
1
available on 40-pin
2
P 3.1-P 3.7, P 4.0
3
pac k ages
P 3
4
5
6
7
P 4
171
0