C8051F564-IMR Silicon Labs, C8051F564-IMR Datasheet - Page 172

• Manufacturer Part Number: C8051F564-IMR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB CAN2.0 LIN 2.1 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F564-IMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051F55x/56x/57x
19.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals.
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Port 4 C8051F568-9 and ‘F570-5 is a
digital-only Port. Any pins to be used as Comparator or ADC inputs should be configured as an analog
inputs. When a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are
disabled. This process saves power and reduces noise on the analog input. Pins configured as digital
inputs may still be used by analog peripherals; however this practice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a
digital input, and a 0 indicates an analog input. All pins default to digital inputs on reset. See SFR Definition
19.13 for the PnMDIN register details.
172
P o r t
S p e c i a l
F u n c t i o n
S i g n a l s
P I N I / O
U A R T _ T X
U A R T _ R X
C A N _ T X
C A N _ R X
S C K
M I S O
M O S I
N S S
S D A
S C L
C P 0
C P 0 A
C P 1
C P 1 A
S Y S C L K
C E X 0
C E X 1
C E X 2
C E X 3
C E X 4
C E X 5
E C I
T 0
T 1
L I N _ T X
L I N _ R X
(PnMDOUT).
0
0
1
1
Figure 19.4. Crossbar Priority Decoder in Example Configuration
P 0 S K I P [0 :7 ]
2
1
3
0
P 0
4
0
5
1
6
0
7
0
0
0
1
0
* N S S Is o n l y p i n n e d o u t i n 4 -w i r e S P I M o d e
P 1 S K I P [ 0 :7 ]
2
0
3
0
P 1
4
0
5
0
Rev. 1.1
6
0
7
0
0
0
1
0
P 2 S K I P [ 0 : 7 ]
a n d 3 2 - p i n p a c k a g e s
2
0
a va i l a b l e o n 4 0 - p i n
P 2 . 2 - P 2 . 7 , P 3 . 0
3
0
P 2
4
0
5
0
6
0
7
0
0
0
1
0
P 3 S K I P [ 0 : 7 ]
a va i l a b l e o n 4 0 - p i n
2
0
P 3 . 1 - P 3 . 7 , P 4 . 0
3
0
p a c k a g e s
P 3
4
0
5
0
6
0
7
0
P 4
0