Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet

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Z8F011ASH020EG2156

Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F011ASH020EG2156

Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V

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Part Number:
Z8F011ASH020EG2156
Manufacturer:
Zilog
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266
High-Performance 8-Bit Microcontrollers
®
Z8 Encore!
F0830 Series
Product Specification
PS025113-1212
®
Copyright ©2012 Zilog
, Inc. All rights reserved.
www.zilog.com

Z8F011ASH020EG2156 Summary of contents

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... High-Performance 8-Bit Microcontrollers ® Z8 Encore! Product Specification PS025113-1212 ® Copyright ©2012 Zilog , Inc. All rights reserved. www.zilog.com F0830 Series ...

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... HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS025113-1212 ® ...

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Revision History Each instance in this document’s revision history reflects a change from its previous edi- tion. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Revision Date Level Chapter/Section Dec 13 GPIO ...

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Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 1. Z8 Encore! F0830 Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure ...

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Figure 27. Typical RC Oscillator Frequency as a Function of External Capacitance with a 45 kΩ Resistor . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables Table 1. Z8 Encore! F0830 Series Family Part Selection Guide . . . . . . . . . . . . . . . . . 2 Table 2. Acronyms and Expansions . . . . ...

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Table 29. Port A–C Input Data Registers (PxIN Table 30. Port ...

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Table 59. Watchdog Timer Control Register (WDTCTL Table 60. Watchdog Timer Reload Upper Byte Register (WDTU ...

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Table 89. Trim Option Bits at 0006H (TCLKFLT 132 Table 90. ClkFlt Delay Control ...

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Table 119. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . 192 Table 120. Watchdog Timer Electrical Characteristics and Timing . . . . . . . ...

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Table 149. ADC Sample Settling Time (ADCSST 215 Table 150. ADC Sample Time (ADCST) ...

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Table 179. Port C Input Data Registers (PCIN 224 Table 180. ...

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... Overview Zilog’s Z8 Encore! MCU family of products are the first in a line of Zilog microcontroller products based on the 8-bit eZ8 CPU. The Z8 Encore! F0830 Series products expand on Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capabil- ity allows for faster development time and program changes in the field. The new eZ8 CPU is upward-compatible with existing Z8 CPU instructions ...

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Part Selection Guide Table 1 lists the basic features available for each device within the Z8 Encore! F0830 Series product line. See Table 1. Z8 Encore! F0830 Series Family Part Selection Guide Part Number Z8F1232 Z8F1233 Z8F0830 Z8F0831 Z8F0430 Z8F0431 ...

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Block Diagram Figure 1 displays a block diagram of the Z8 Encore! F0830 Series architecture eZ8 CPU Memory Bus Register Bus Timers Comparator GPIO Figure 1. Z8 Encore! F0830 Series Block Diagram PS025113-1212 System Oscillator Clock Control On-Chip Debugger Interrupt ...

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... CPU and Peripheral Overview The eZ8 CPU, Zilog’s latest 8-bit CPU, meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The eZ8 CPU features include: • Direct register-to-register architecture allows each register to function as an accumula- tor, improving execution time and decreasing the required program memory • ...

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Nonvolatile Data Storage The Nonvolatile Data Storage (NVDS) function uses a hybrid hardware/software scheme to implement a byte-programmable data memory and is capable of storing about 100,000 write cycles. Internal Precision Oscillator The Internal Precision Oscillator (IPO) function, with an ...

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Reset Controller The Z8 Encore! F0830 Series products are reset using any one of the following: the RESET pin, Power-On Reset, Watchdog Timer (WDT) time-out, STOP Mode exit or Volt- age Brown-Out (VBO) warning signal. The RESET pin is bidirectional; ...

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Pin Description The Z8 Encore! F0830 Series products are available in a variety of package styles and pin configurations. This chapter describes the signals and the pin configurations for each of the package styles. For information about the physical package ...

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The analog supply pins (AV replaced by PB6 and PB7. At reset, by default, all pins of Port A, B and C are in Input state. The alternate functional- ity is also disabled, so the pins function as general purpose ...

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PC3/COUT/LED 16 PB0/ANA0 17 PB1/ANA1 18 PB2/ANA2 19 PB3/CLKIN/ANA3 20 Figure 4. Z8F0830 Series in 20-Pin QFN Package PS025113-1212 PA7/T1OUT PA7/T1OUT 10   PA6/T1IN/T1OUT PA6/T1IN/T1OUT 9   PA5 PA5 8   20-Pin QFN PA4 PA4 7  ...

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PC3/COUT/LED PB0/ANA0 PB1/ANA1 PB2/ANA2 PB4/ANA7 PB5/V REF PB3/CLKIN/ANA3 Figure 5. Z8F0830 Series in 28-Pin QFN Package PS025113-1212 28-Pin QFN ...

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Signal Descriptions Table 4 describes the Z8 Encore! F0830 Series signals. See the on page 7 to determine the signals available for each specific package style. Signal Mnemonic I/O Description General-Purpose I/O Ports A–D PA[7:0] I/O Port A. These pins ...

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Table 4. Signal Descriptions (Continued) Signal Mnemonic I/O Description Oscillators X I External crystal input. This is the input pin to the crystal oscillator. A crystal IN can be connected between it and the XOUT pin to form the oscillator. ...

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Pin Characteristics Table 5 provides detailed characteristics of each pin available on the Z8 Encore! F0830 Series 20- and 28-pin devices. Data in Table 5 are sorted alphabetically by the pin symbol mnemonic. Table 5. Pin Characteristics (20- and 28-pin ...

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... The following sections describe these three address spaces. For more information about the eZ8 CPU and its address space, refer to the which is available for download at www.zilog.com. Register File The register file address space in the Z8 Encore! MCU (4096 bytes). The register file consists of two sections: control registers and general-purpose registers ...

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Program Memory The eZ8 CPU supports program memory address space. The Z8 Encore! F0830 Series devices contain on-chip Flash memory in the program memory address space, depending on the device. Reading ...

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... FE00–FE3F FE40–FE53 FE54–FE5F FE60–FE7F FE80–FFFF PS025113-1212 to . When information area access is enabled, all FE00H FE7FH Function Zilog option bits Part Number 20-character ASCII alphanumeric code Left-justified and filled with FH Reserved Reserved Reserved ® Z8 Encore! F0830 Series Product Specification ...

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Register Map Table 8 provides an address map of the Z8 Encore! F0830 Series register file. Not all devices and package styles in the Z8 Encore! F0830 Series support the ADC or all of the GPIO ports. Consider registers for ...

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Table 8. Register File Address Map (Continued) Address (Hex) Register Description Analog-to-Digital Converter (ADC, cont’d) F73 ADC data low bits F74 ADC sample settling time F75 ADC sample time F76 Reserved F77–F7F Reserved Low Power Control F80 Power control 0 ...

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Table 8. Register File Address Map (Continued) Address (Hex) Register Description Interrupt Controller (cont’d) FCE Shared interrupt select FCF Interrupt control GPIO Port A FD0 Port A address FD1 Port A control FD2 Port A input data FD3 Port A ...

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Table 8. Register File Address Map (Continued) Address (Hex) Register Description Trim Bit Control FF6 Trim bit address FF7 Trim data Flash Memory Controller FF8 Flash control FF8 Flash status FF9 Flash page select Flash sector protect FFA Flash programming ...

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Reset and Stop Mode Recovery The reset controller in the Z8 Encore! F0830 Series controls RESET and Stop Mode Recovery operations typical operation, the following events can cause a reset: • Power-On Reset (POR) • Voltage Brown-Out (VBO) ...

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Table 9. Reset and Stop Mode Recovery Characteristics and Latency Reset Type Control Registers System Reset Reset (as applicable) System Reset with Crystal Reset (as applicable) Oscillator Enabled Stop Mode Recovery Unaffected, except WDT_CTL and OSC_CTL registers Stop Mode Recovery ...

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Reset Sources Table 10 lists the possible sources of a system reset. Table 10. Reset Sources and Resulting Reset Type Operating Mode Reset Source NORMAL or HALT Power-On Reset/Voltage Brown-Out Reset delay begins after supply voltage modes Watchdog Timer time-out ...

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V POR V VBO VDD = 0.0V Internal Precision Oscillator Crystal Oscillator Internal RESET signal Note: Not to Scale Voltage Brown-Out Reset The devices in the Z8 Encore! F0830 Series provide low Voltage Brown-Out (VBO) pro- tection. The VBO circuit ...

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The Voltage Brown-Out circuit can be either enabled or disabled during STOP Mode. Operations during STOP Mode is set by the VBO_AO Flash option bit. See the Option Bits chapter on page 124 for information about configuring VBO_AO ...

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A reset pulse of three clock cycles in duration might trigger a reset and a reset pulse of four cycles in duration always triggers a ...

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The eZ8 CPU fetches the reset vector at program memory addresses and loads that value into the program counter. Program execution begins at the reset vector address. Following Stop Mode Recovery, the STOP bit in the Reset Status (RSTSTAT) Register ...

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Stop Mode Recovery Using the External RESET Pin When the Z8 Encore! F0830 Series device is in STOP Mode and the external RESET pin is driven low, a system reset occurs. Because of a glitch filter operating on the RESET ...

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Table 12. Reset Status Register (RSTSTAT) Bit 7 6 Field POR STOP RESET See Table 13 R Address Bit Description [7] Power-On Reset Indicator POR This bit is set Power-On Reset event occurs and ...

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Low-Power Modes The Z8 Encore! F0830 Series products contain power saving features. The highest level of power reduction is provided by the STOP Mode. The next level of power reduction is pro- vided by the HALT Mode. Further power savings ...

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HALT Mode Executing the eZ8 CPU HALT instruction places the device into HALT Mode. In HALT Mode, the operating characteristics are: • Primary oscillator is enabled and continues to operate • System clock is enabled and continues to operate • ...

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Note: This register is only reset during a Power-On Reset sequence. Other system reset events do not affect it. Table 14. Power Control Register 0 (PWRCTL0) Bit 7 6 Field Reserved RESET 1 0 R/W R/W R/W Address Bit Description ...

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General Purpose Input/Output The Z8 Encore! F0830 Series products support a maximum of 25 port pins (Ports A–D) for General Purpose Input/Output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output ...

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Architecture Figure 8 displays a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions and variable port current drive strength is not dis- played. System Port Output Data Register DATA D Q ...

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PA0 and PA6 contain two different Timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the TIMER mode. For more details, see ...

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External Clock Setup For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin devices. In this case, configure PB3 for Alternate function CLKIN. Write to the Oscillator Control Register (see the select the PB3 ...

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Table 16. Port Alternate Function Mapping (Continued) Port Pin Mnemonic 2 Port B PB0 Reserved ANA0 PB1 Reserved ANA1 PB2 Reserved ANA2 PB3 CLKIN ANA3 PB4 Reserved ANA7 PB5 Reserved V REF PB6 Reserved Reserved PB7 Reserved Reserved Notes: 1. ...

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Table 16. Port Alternate Function Mapping (Continued) Port Pin Mnemonic 3 Port C PC0 Reserved ANA4/CINP PC1 Reserved ANA5/CINN PC2 Reserved ANA6 PC3 COUT Reserved PC4 Reserved PC5 Reserved PC6 Reserved PC7 Reserved 1 Port D PD0 RESET Notes: 1. ...

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GPIO Interrupts Many of the GPIO port pins can be used as interrupt sources. Some port pins can be con- figured to generate an interrupt request on either the rising edge or falling edge of the input pin signal. Other ...

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Port A–D Address Registers The Port A–D Address registers select the GPIO port functionality accessible through the Port A–D Control registers. The Port A–D Address and Control registers combine to pro- vide access to all GPIO port controls; see Tables ...

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Port A–D Control Registers The Port A–D Control registers, shown in Table 20, set the GPIO port operation. The value in the corresponding Port A–D Address Register determines which subregister is read from or written Port A–D ...

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Port A–D Alternate Function Subregisters The Port A–D Alternate Function Subregister is accessed through the Port A–D Control Register by writing Port A–D Alternate Function subregisters enable the alternate function selection on pins. If disabled, the pins function as GPIOs. ...

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Port A–D Output Control Subregisters The Port A–D Output Control Subregister, shown in Table 23, is accessed through the Port A–D Control Register by writing the Port A–D Output Control subregisters to 1 configures the specified port pins for open- ...

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Port A–D High Drive Enable Subregisters The Port A–D High Drive Enable Subregister, shown in Table 24, is accessed through the Port A–D Control Register by writing bits in the Port A–D High Drive Enable subregisters to 1 configures the ...

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Port A–D Stop Mode Recovery Source Enable Subregisters The Port A–D Stop Mode Recovery Source Enable Subregister, shown in Table 25, is accessed through the Port A–D Control Register by writing Register. Setting the bits in the Port A–D Stop ...

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Port A–D Pull-up Enable Subregisters The Port A–D Pull-Up Enable Subregister is accessed through the Port A–D Control Reg- ister by writing 06H Port A–D Pull-Up Enable subregisters enables a weak internal resistive pull-up on the specified port pins. Table ...

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Port A–D Alternate Function Set 1 Subregisters The Port A–D Alternate Function Set 1 Subregister, shown in Table 27, is accessed through the Port A–D Control Register by writing The Alternate Function Set 1 subregisters select the alternate function available ...

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Port A–D Alternate Function Set 2 Subregisters The Port A–D Alternate Function Set 2 Subregister, shown in Table 28, is accessed through the Port A–D Control Register by writing The Alternate Function Set 2 subregisters select the alternate function available ...

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Port A–C Input Data Registers Reading from the Port A–C Input Data registers, shown in Table 29, return the sampled values from the corresponding port pins. The Port A–C Input Data registers are read-only. The value returned for any unused ...

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Port A–D Output Data Register The Port A–D Output Data Register, shown in Table 30, controls the output data to the pins. Table 30. Port A–D Output Data Register (PxOUT) Bit 7 6 Field POUT7 POUT6 RESET 0 0 R/W ...

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LED Drive Enable Register The LED Drive Enable Register, shown in Table 31, activates the controlled current drive. The Alternate Function Register has no control over the LED function; therefore, setting the Alternate Function Register to select the LED function ...

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LED Drive Level Low Register The LED Drive Level Low Register, shown in Table 33, contains two control bits for each Port C pin. These two bits select one of four programmable current drive levels for each Port C pin. ...

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... The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the Interrupt Controller has no effect on operation. For more information about interrupt servicing by the eZ8 CPU, refer to the able for download at www.zilog.com. Interrupt Vector Listing Table 34 lists the interrupts available in order of priority. The interrupt vector is stored with the most significant byte (MSB) at the even program memory address and the least significant byte (LSB) at the odd program memory address ...

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Table 34. Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset (not an interrupt) 0004H Watchdog Timer (see Watchdog Timer chapter) 003AH Primary oscillator fail trap (not an interrupt) ...

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Architecture Figure 9 displays the Interrupt Controller block diagram. Port Interrupts Internal Interrupts Figure 9. Interrupt Controller Block Diagram Operation This section describes the operational aspects of the following functions. Master Interrupt Interrupt Vectors and Interrupt Assertion: see page 56 ...

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... Caution: Zilog recommends not using a coding style that clears bits in the Interrupt Request reg- isters. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. See Example 1, which follows. ...

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... CPU, the bit in the interrupt request register is automatically cleared to 0. Caution: Zilog recommends not using a coding style to generate software interrupts by setting bits in the Interrupt Request registers. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. See Example 3, which fol- lows ...

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Interrupt Request 0 Register The Interrupt Request 0 (IRQ0) Register, shown in Table 35 stores the interrupt requests for both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the corresponding bit in the IRQ0 Register ...

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Interrupt Request 1 Register The Interrupt Request 1 (IRQ1) Register, shown in Table 36, stores interrupt requests for both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the corresponding bit in the IRQ1 Register becomes ...

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Interrupt Request 2 Register The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the corresponding bit in the IRQ2 Register becomes ...

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Table 39. IRQ0 Enable High Bit Register (IRQ0ENH) Bit 7 6 Field Reserved T1ENH RESET 0 0 R/W R/W R/W Address Bit Description [7] Reserved This bit is reserved and must be programmed to 0. [6] Timer 1 Interrupt Request ...

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IRQ1 Enable High and Low Bit Registers Table 41 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg- isters, shown in Tables 42 and 43, form a priority-encoded enabling service for interrupts in the Interrupt ...

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Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL) Bit 7 6 Field PA7ENL PA6CENL RESET 0 0 R/W R/W R/W Address Bit Description [7] Port A Bit[7] Interrupt Request Enable Low Bit PA7ENL [6] Port A Bit[7] or Comparator Interrupt ...

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Table 45. IRQ2 Enable High Bit Register (IRQ2ENH) Bit 7 6 Field Reserved RESET 0 0 R/W R/W R/W Address Bit Description [7:4] Reserved These registers are reserved and must be programmed to 0000. [3] Port C3 Interrupt Request Enable ...

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Interrupt Edge Select Register The interrupt edge select (IRQES) register determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port A or Port D input pin. See Table 47. Table 47. Interrupt ...

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Shared Interrupt Select Register The shared interrupt select (IRQSS) register determines the source of the PADxS inter- rupts. See Table 48. The shared interrupt select register selects between Port A and alter- nate sources for the individual interrupts. Because these ...

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Interrupt Control Register The Interrupt Control (IRQCTL) Register, shown in Table 49, contains the master enable bit for all interrupts. Table 49. Interrupt Control Register (IRQCTL) Bit 7 6 Field IRQE RESET 0 0 R/W R/W R Address Bit Description ...

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Timers The Z8 Encore! F0830 Series products contain up to two 16-bit reloadable timers that can be used for timing, event counting or generation of pulse width modulated (PWM) signals. The timers feature include: • 16-bit reload counter • Programmable ...

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Data Bus Block Control System Clock Timer Input Gate Input Capture Input Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value into the Timer Reload High and Low Byte registers and setting the prescale ...

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For the timer output to make a state change at a ONE-SHOT time-out (rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value before enabling ONE-SHOT Mode. After starting ...

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Disable the timer Configure the timer for CONTINUOUS Mode – – Set the prescale value If using the timer output Alternate function, set the initial output level (High or – Low) 2. Write to the Timer High and Low ...

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Low to High or from High to Low) at timer reload. Observe the following steps for configuring a timer for COUNTER Mode and for initiat- ing the count: 1. Write to ...

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Caution: The frequency of the comparator output signal must not exceed one-fourth the system clock frequency. After reaching the reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in ...

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PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT Mode, the timer outputs a pulse width modulated (PWM) output signal through a GPIO port pin. The timer input is the system clock. The timer first counts up to 16-bit PWM match ...

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PWM Period ( initial starting value other than registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period. If TPOL bit is set to 0, the ratio of the PWM output high time to the ...

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Observe the following steps for configuring a timer for PWM DUAL OUTPUT Mode and for initiating the PWM operation: 1. Write to the Timer Control Register to: Disable the timer – Configure the timer for PWM DUAL OUTPUT Mode; setting ...

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PWM Output High Time Ratio (%) If is set to 1, the ratio of the PWM output high time to the total period is represented TPOL by: PWM Output High Time Ratio (%) CAPTURE Mode In CAPTURE Mode, the current ...

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Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and Reload events. If appropriate, configure the timer interrupt ...

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Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Clear the timer PWM High and Low Byte registers to ware to determine if interrupts are generated by either a capture event or ...

Page 98

Enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers using the timer output function, configure the associated GPIO port pin for the timer output alternate function. 6. Write to ...

Page 99

The user can configure the timer interrupt to be generated only at the input deassertion event or the reload event by setting the TICONFIG field of the TxCTL1 Register. 5. Configure the associated GPIO port pin ...

Page 100

Write to the Timer Control Register to enable the timer. 7. Counting begins on the first appropriate transition of the timer input signal. No inter- rupt is generated by the first edge. In CAPTURE/COMPARE Mode, the elapsed time from ...

Page 101

Timer Control Register Definitions This section defines the features of the following Timer Control registers. Timer 0–1 High and Low Byte Timer Reload High and Low Byte Timer 0–1 PWM High and Low Byte Timer 0–1 Control Timer 0–1 High ...

Page 102

Bit Description [7:0] Timer High and Low Bytes TH, TL These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value. PS025113-1212 ® Z8 Encore! F0830 Series Product Specification Timer Control Register Definitions 84 ...

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Timer Reload High and Low Byte Registers The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) registers, shown in Tables 52 and 53, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte ...

Page 104

Timer 0–1 PWM High and Low Byte Registers The Timer 0–1 PWM High and Low Byte (TxPWMH and TxPWML) registers, shown in Tables 54 and 55, control PWM operations. These registers also store the capture values for the CAPTURE and ...

Page 105

Timer 0–1 Control Registers The Timer Control registers are 8-bit read/write registers that control the operation of their associated counter/timers. Time 0–1 Control Register 0 The Timer Control 0 (TxCTL0) and Timer Control 1 (TxCTL1) registers determine the timer operating ...

Page 106

Bit Description (Continued) [0] Input Capture Event INPCAP This bit indicates whether the most recent timer interrupt is caused by a timer input capture event Previous timer interrupt is not caused by timer input capture event ...

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Bit Description (Continued) [6] Timer Input/Output Polarity TPOL Operation of this bit is a function of the current operating mode of the timer. ONE-SHOT Mode When the timer is disabled, the timer output signal is set to the value of ...

Page 108

Bit Description (Continued) [6] PWM DUAL OUTPUT Mode TPOL 0 = Timer output is forced Low (0) and timer output complement is forced High (1), when the (cont’d) timer is disabled. When enabled and the PWM count matches, the timer ...

Page 109

Bit Description (Continued) [2:0] Timer Mode TMODE This field along with the TMODEHI bit in TxCTL0 register determines the operating mode of the timer. TMODEHI is the most significant bit of the timer mode selection value. 0000 = ONE-SHOT Mode. ...

Page 110

Watchdog Timer The Watchdog Timer (WDT) protects from corrupted or unreliable software, power faults and other system-level problems which can place the Z8 Encore! F0830 Series devices into unsuitable operating states. The features of the Watchdog Timer include: • On-chip ...

Page 111

Watchdog Timer Refresh Upon first enable, the Watchdog Timer is loaded with the value in the Watchdog Timer Reload registers. The Watchdog Timer counts down to tion is executed by the eZ8 CPU. Execution of the WDT instruction causes the ...

Page 112

WDT Reset in Normal Operation If configured to generate a reset when a time-out occurs, the Watchdog Timer forces the device into the System Reset state. The WDT status bit in the Watchdog Timer Control Register is set to 1. ...

Page 113

Watchdog Timer Control Register Definitions This section defines the features of the following Watchdog Timer Control registers. Watchdog Timer Control Register Watchdog Timer Reload Low Byte Register Watchdog Timer Reload Upper Byte Register Watchdog Timer Reload High Byte Register Watchdog ...

Page 114

Watchdog Timer Reload Upper, High and Low Byte Registers The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) regis- ters, shown in Tables 60 through 62, form the 24-bit reload value that is loaded into the Watchdog ...

Page 115

Table 62. Watchdog Timer Reload Low Byte Register (WDTL) Bit 7 6 Field RESET 0 0 R/W R/W* R/W* Address Note: *A read returns the current WDT count value; a write sets the appropriate reload value. Bit Description [7:0] WDT ...

Page 116

Analog-to-Digital Converter The Z8 Encore! MCU includes an eight-channel Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The ADC converts an analog input signal to a 10-bit binary number. The features of the SAR ADC include: • Eight analog input sources ...

Page 117

Internal Voltage Reference Generator Analog-to-Digital Converter Reference Input 10 Data Output Analog Input BUSY ADCLK ADCEN START Figure 11. Analog-to-Digital Converter Block Diagram Operation The ADC converts the analog input, ANA tion for calculating the digital value is represented by: ...

Page 118

ADC Timing Each ADC measurement consists of three phases: 1. Input sampling (programmable, minimum of 1.0 µs) 2. Sample-and-hold amplifier settling (programmable, minimum of 0.5 µs) 3. Conversion is 13 ADCLK cycles Figures 12 and 13 display the timing of ...

Page 119

ADC Interrupt The ADC can generate an interrupt request when a conversion has been completed. An interrupt request that is pending when the ADC is disabled is not cleared automatically. Reference Buffer The reference buffer, RBUF, supplies the reference voltage ...

Page 120

ADC Control Register 0 The ADC Control 0 Register, shown in Table 63, initiates an A/D conversion and provides ADC status information. Table 63. ADC Control Register 0 (ADCCTL0) Bit 7 6 Field START Reserved RESET 0 0 R/W R/W1 ...

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ADC Data High Byte Register The ADC Data High Byte Register, listed in Table 64, contains the upper eight bits of the ADC output. Access to the ADC Data High Byte Register is read-only. Reading the ADC Data High Byte ...

Page 122

Sample Settling Time Register The Sample Settling Time Register, shown in Table 66, is used to program a delay after the SAMPLE/HOLD signal is asserted and before the START signal is asserted; an ADC conversion then begins. The number of ...

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Sample Time Register The Sample Time Register, shown in Table 67, is used to program the length of active time for a sample after a conversion has begun by setting the START bit in the ADC Control Register. The number ...

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... The comparator can be powered down to save supply current. For details, see the Control Register 0 Caution result of the propagation delay of the comparator, Zilog does not recommend en- abling the comparator without first disabling interrupts and waiting for the comparator output to settle. This delay prevents spurious interrupts after comparator enabling. ...

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Comparator Control Register Definitions The Comparator Control Register (CMP0) configures the comparator inputs and sets the value of the internal voltage reference. The GPIO pin is always used as positive compara- tor input. Table 68. Comparator Control Register (CMP0) Bit ...

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Flash Memory The products in the Z8 Encore! F0830 Series features either 1 KB (1024 bytes with NVDS (2048 bytes with NVDS (4096 bytes with NVDS (8192 bytes with NVDS (12288 ...

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Sector 3 0600H 05FFH Sector 2 0400H 03FFH Sector 1 0200H 01FFH Sector 0 0000H 0FFFH Sector 7 0E00H 0DFFH Sector 6 0C00H 0BFFH Sector 5 0A00H 09FFH Sector 4 0800H 07FFH Sector 3 0600H 05FFH Sector 2 0400H ...

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Sector 7 1C00H 18FFH Sector 6 1800H 17FFH Sector 5 1400H 13FFH Sector 4 1C00H 0FFFH Sector 3 0C00H 0BFFH Sector 2 0800H 07FFH Sector 1 0400H 03FFH Sector 0 0000H PS025113-1212 Figure 17. 8K Flash with NVDS ® ...

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... Data Memory Address Space The Flash information area, including Zilog Flash option bits, are located in the data mem- ory address space. The Z8 Encore! MCU is configured by these proprietary Flash option bits to prevent the user from writing to the eZ8 CPU data memory address space. ...

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... The trim bits are handled differently than the other Zilog Flash option bits. The trim bits are the hybrid of the user option bits and the standard Zilog option bits. These trim bits must be user-accessible for reading at all times using external registers regardless of the state of bit 7 in the Flash Page Select Register ...

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Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Write FCTL No 8CH Yes Write Page Select Register No Page Select values match? Yes Yes Page in Protected Sector? No Page Unlocked Program/Erase ...

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Flash Operation Timing Using the Flash Frequency Registers Before performing either a Program or Erase operation on Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash frequency registers allow programming and erasing ...

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Table 71. Flash Code Protection using the Flash Option Bits FHSWP FWP Flash Code Protection Description 0 0 Programming and erasing disabled for all Flash program memory. In user code pro- gramming, page erase and mass erase are all disabled. ...

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... The byte at each address within Flash memory cannot be programmed (any bits written to 0) more than twice before an erase cycle occurs. PS025113-1212 to the Flash Control Register deselects 5EH . (UM0128), which is available for download on www.zilog.com, for the and instructions. While the Flash Controller programs the LDC LDCI ® ...

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... Page Erase operations are also supported, when the Flash Controller is bypassed. For more information about bypassing the Flash Controller, refer to Third-Party Flash Programming Support for Z8 Encore!. This document is available for download at www.zilog.com. Flash Controller Behavior in Debug Mode The following behavioral changes can be observed in the Flash Controller when the Flash Controller is accessed using the On-Chip Debugger: • ...

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... The device uses Flash memory space, despite the maximum specified Flash size (with the exception mode with non-NVDS). User code accesses the lower Flash, leaving the upper 4 KB for proprietary (for Zilog-only) memory. The NVDS is implemented by using this proprietary memory space for special-purpose rou- tines and for the data required by these routines, which are factory-programmed and can- not be altered by the user ...

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Flash Control Register The Flash Controller must be unlocked using the Flash Control Register before program- ming or erasing Flash memory. Writing the sequence Control Register unlocks the Flash Controller. When the Flash Controller is unlocked, Flash memory can be ...

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Flash Status Register The Flash Status Register indicates the current state of the Flash Controller. This register can be read at any time. The read-only Flash Status Register shares its register file address with the write-only Flash Control Register. Table ...

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Flash Page Select Register The Flash Page Select Register shares address space with the Flash Sector Protect Regis- ter. Unless the Flash Controller is locked and written with will target the Flash Page Select Register. The register selects one of ...

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Flash Sector Protect Register The Flash Sector Protect Register is shared with the Flash Page Select Register. When the Flash Control Register is locked and written with gets the Flash Sector Protect Register. In all other cases, it targets the ...

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Flash Frequency High and Low Byte Registers The Flash Frequency High and Low Byte registers, shown in Tables 76 and 77, combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit binary ...

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Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore! F0830 Series operation. The feature configuration data is stored in the Flash program memory and read during reset. The features available for control through ...

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Option Bit Types This section describes the two types of Flash option bits offered in the F0830 Series. User Option Bits The user option bits are contained in the first two bytes of program memory. User access to these bits ...

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Flash Option Bit Control Register Definitions This section briefly describes the features of the Trim Bit Address and Data registers. Trim Bit Address Register The Trim Bit Address Register, shown in Table 78, contains the target address to access the ...

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Table 80. Trim Bit Data Register (TRMDR) Bit 7 6 Field RESET 0 0 R/W R/W R/W Address Flash Option Bit Address Space The first two bytes of Flash program memory at addresses for the user-programmable Flash option bits. See ...

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Bit Description (Continued) [3] Voltage Brown-Out Protection Always On VBO_AO 0 = Voltage Brown-Out protection is disabled in STOP Mode to reduce total power con- sumption Voltage Brown-Out protection is always enabled, even during STOP Mode. This setting ...

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Bit Description (Continued) [4] State of the Crystal Oscillator at Reset XTLDIS This bit enables only the crystal oscillator. Selecting the crystal oscillator as the system clock must be performed manually The crystal oscillator is enabled during reset, ...

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Address 00h 01h 02h 03h 06h Table 84. Trim Option Bits at 0000H (ADCREF) Bit 7 6 Field ADCREF_TRIM RESET R/W Address Note Unchanged by Reset. R/W = Read/Write. Bit Description [7:3] ADC Reference Voltage Trim Byte ADCREF_TRIM ...

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Note: The bit values used in Table 85 are set at the factory; no calibration is required. Table 86. Trim Option Bits at 0002H (TIPO) Bit 7 6 Field RESET R/W Address Note Unchanged by Reset. R/W = ...

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Note: The bit values used in Table 87 are set at the factory; no calibration is required. On-chip Flash memory is only guaranteed to perform write operations when voltage sup- plies exceed 2.7 V. Write operations at voltages below 2.7 ...

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Bit Description (Continued) [1:0] Filter Select FilterSely 2-bit selection for the clock filter mode filter Filter low level noise on high level signal Filter high level noise on low level signal ...

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... Flash 12 KB mode). This type of memory can perform over 100,000 write cycles. Operation NVDS is implemented by special-purpose Zilog software stored in areas of program mem- ory that are not user-accessible. These special-purpose routines use Flash memory to store the data, and incorporate a dynamic addressing scheme to maximize the write/erase endur- ance of the Flash ...

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Byte Write To write a byte to the NVDS array, the user code must first push the address, then the data byte onto the stack. The user code issues a Write routine ( 0x20B3 working register R0. The bit fields ...

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Byte Read To read a byte from the NVDS array, user code must first push the address onto the stack. User code issues a the return from the subroutine, the read byte resides in working register R0 and the read ...

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Power Failure Protection NVDS routines employ error-checking mechanisms to ensure that any power failure will only endanger the most recently written byte. Bytes previously written to the array are not perturbed. For this protection to function, the VBO must be ...

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Because the minimum read time is much less than the write time, however, actual speed benefits are not always realized. 2. Use as few unique addresses as possible to optimize the impact of refreshing. PS025113-1212 ® Z8 Encore! F0830 Series ...

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On-Chip Debugger The Z8 Encore! devices contain an integrated On-Chip Debugger (OCD) that provides the following advanced debugging features: • Reading and writing of the register file • Reading and writing of program and data memory • Setting of breakpoints ...

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Operation The following section describes the operation of the On-Chip Debugging function. OCD Interface The On-Chip Debugger uses the DBG pin for communication with an external host. This one-pin interface is a bidirectional open-drain interface that transmits and receives data. ...

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RS-232 TX RS-232 RX Figure 22. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface DEBUG Mode The operating characteristics of the devices in DEBUG Mode are: • The eZ8 CPU fetch unit stops, idling the ...

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Watchdog Timer reset • Asserting the RESET pin Low to initiate a reset • Driving the DBG pin Low while the device is in STOP Mode initiates a system reset OCD Data Format The OCD interface uses the asynchronous ...

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If the OCD receives a serial break (nine or more continuous bits low), the autobaud detec- tor/generator resets. Reconfigure the autobaud detector/generator by sending OCD Serial Errors The OCD can detect any of the following error conditions on the DBG ...

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Runtime Counter The OCD contains a 16-bit runtime counter. It counts system clock cycles between break- points. The counter starts counting when the OCD leaves DEBUG Mode and stops count- ing when it enters DEBUG Mode again or when it ...

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Table 95. On-Chip Debugger Command Summary (Continued) Command Debug Command Read Program Memory CRC Reserved Step Instruction Stuff Instruction Execute Instruction Reserved 13H–FFH In the following bulleted list of OCD commands, data and commands sent from the host to the ...

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Read OCD Control Register (05H). value of the OCDCTL register. ← DBG 05H → DBG OCDCTL[7:0] Write Program Counter (06H). follows to the eZ8 CPU’s program counter (PC). If the device is not in DEBUG Mode or if the Flash ...

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DBG 0AH ← DBG Program Memory Address[15:8] ← DBG Program Memory Address[7:0] ← DBG Size[15:8] ← DBG Size[7:0] ← DBG 1–65536 data bytes Read Program Memory (0BH). program memory. This command is equivalent to the LDC and LDCI instructions. ...

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DBG 0EH → DBG CRC[15:8] → DBG CRC[7:0] Step Instruction (10H). the current program counter (PC) location. If the ...

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Table 96. OCD Control Register (OCDCTL) Bit 7 6 Field DBGMODE BRKEN RESET 0 0 R/W R/W R/W Bit Description [7] DEBUG Mode DBGMODE The device enters DEBUG Mode when this bit is 1. When in DEBUG Mode, the eZ8 ...

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OCD Status Register The OCD Status Register reports status information about the current state of the debugger and the system. Table 97. OCD Status Register (OCDSTAT) Bit 7 6 Field DBG HALT RESET Bit Description ...

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Oscillator Control The Z8 Encore! F0830 Series device uses five possible clocking schemes. Each one of these is user-selectable. • On-chip precision trimmed RC oscillator • On-chip oscillator using off-chip crystal or resonator • On-chip oscillator using external RC network ...

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Table 98. Oscillator Configuration and Selection Clock Source Characteristics Internal precision • 32.8 kHz or 5.53 RC oscillator • ± 4% accuracy when trimmed • No external components required External crystal/res- • 32 kHz to 20 MHz onator • Very ...

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When selecting a new clock source, the primary oscillator failure detection circuitry and the Watchdog Timer Oscillator failure circuitry must be disabled. If POFEN and WOFEN are not disabled prior to a clock switch-over possible to generate an ...

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Caution possible to disable the clock failure detection circuitry as well as all functioning clock sources. In this case, the Z8 Encore! F0830 Series device ceases functioning and can only be recovered by power-on-reset. Oscillator Control Register Definitions ...

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Bit Description (Continued) [4] Primary Oscillator Failure Detection Enable POFEN 1 = Failure detection and recovery of primary oscillator is enabled Failure detection and recovery of primary oscillator is disabled. [3] Watchdog Timer Oscillator Failure Detection Enable WDFEN ...

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NO Switch to OSC? YES NO OSC is enabled? Set bit6 in OSCCTL register and wait YES 1.5ms@20MHz Write to OSCCTL register unlock OSCCTL register Write to OSCCTL register: 010 to bits [2:0] Figure 24. Oscillator Control ...

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Crystal Oscillator The products in the Z8 Encore! F0830 Series contain an on-chip crystal oscillator for use with external crystals with 32 kHz to 20 MHz frequencies. In addition, the oscillator sup- ports external RC networks with oscillation frequencies up ...

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IPO cycles for the crystal to stabilize. After this period, the crystal oscillator may be selected as the system clock. Figure 25 displays a recommended configuration for connection with an external ...

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Oscillator Operation with an External RC Network Figure 26 displays a recommended configuration for connection with an external resistor- capacitor (RC) network. Figure 26. Connecting the On-Chip Oscillator to an External RC Network An external resistance value of 45 kΩ ...

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4000 3750 3500 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 250 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 ...

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Internal Precision Oscillator The Internal Precision Oscillator (IPO) is designed for use without external components. The user can either manually trim the oscillator for a nonstandard frequency or use the automatic factory-trimmed version to achieve a 5.53 MHz frequency with ...

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CPU Instruction Set This chapter describes the following features of the eZ8 CPU instruction set: Assembly Language Programming Assembly Language eZ8 CPU Instruction eZ8 CPU Instruction eZ8 CPU Instruction Assembly Language Programming Introduction The eZ8 CPU assembly language provides ...

Page 181

Assembly Language Source Program Example JP START START 234H, #%01 Assembly Language Syntax For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as destination, source. After assembly, the object code ...

Page 182

Example 2 In general, when an instruction format requires an 8-bit register address, the address can specify any register location in the range 0–255 or, using escaped mode addressing, a working register R0–R15. If the contents of register added and ...

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Table 103. Notational Shorthand (Continued) Notation Description R Register RA Relative Address rr Working Register Pair RR Register Pair Vector Vector Address X Indexed Table 104 contains additional symbols that are used throughout the instruction summary and instruction set description ...

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This example indicates that the source data is added to the destination data; the result is stored in the destination location. eZ8 CPU Instruction Classes eZ8 CPU instructions can be divided functionally into the following groups: • Arithmetic • Bit ...

Page 185

Table 105. Arithmetic Instructions (Continued) Mnemonic Operands INCW dst MULT dst SBC dst, src SBCX dst, src SUB dst, src SUBX dst, src Table 106. Bit Manipulation Instructions Mnemonic Operands BCLR bit, dst BIT p, bit, dst BSET bit, dst ...

Page 186

Mnemonic ATM CCF DI EI HALT NOP RCF SCF SRP STOP WDT Mnemonic Operands CLR dst LD dst, src LDC dst, src LDCI dst, src LDE dst, src LDEI dst, src LDWX dst, src LDX dst, src LEA dst, X(src) ...

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Mnemonic Operands AND dst, src ANDX dst, src COM dst OR dst, src ORX dst, src XOR dst, src XORX dst, src Table 111. Program Control Instructions Mnemonic Operands BRK — BTJ p, bit, src, DA BTJNZ bit, src, DA ...

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Table 112. Rotate and Shift Instructions (Continued) Mnemonic RR RRC SRA SRL SWAP PS025113-1212 Operands Instruction dst Rotate Right dst Rotate Right through Carry dst Shift Right Arithmetic dst Shift Right Logical dst Swap Nibbles ® Z8 Encore! F0830 Series ...

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CPU Instruction Summary Table 113 summarizes the eZ8 CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch and the ...

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Table 113. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst AND src AND dst, src ANDX dst, src dst ← dst AND src ATM Block all interrupt and DMA requests during execution of the next 3 ...

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Table 113. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← 00H CLR dst dst ← ~dst COM dst CP dst, src dst - src CPC dst, src dst - src - C CPCX dst, src dst - ...

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Table 113. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst – 1 DJNZ dst dst  0 PC ← IRQCTL[7] ← HALT HALT Mode dst ← dst + 1 ...

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Table 113. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← src LD dst, rc dst ← src LDC dst, src dst ← src LDCI dst, src r ← 1 rr ← dst ...

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Table 113. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← src LDX dst, src LEA dst, X(src) dst ← src + X dst[15:0] ←  MULT dst dst[15:8] * dst[7:0] NOP No operation dst ← dst OR ...

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Table 113. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← @SP POPX dst SP ← ← SP – 1 PUSH src @SP ← src SP ← SP – 1 PUSHX src @SP ← ...

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Table 113. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation SRA dst dst SRL dst dst RP ← src SRP src STOP ...

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Table 113. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation TM dst, src dst AND src TMX dst, src dst AND src SP ← SP – 2 TRAP Vector @SP ← PC SP ← SP – 1 @SP ← ...

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Op Code Maps A description of the opcode map data and the abbreviations are provided in Figure 28. Table 114 on page 181 lists opcode map abbreviations. Op Code Upper Nibble Figure 28. Op Code Map Cell Description PS025113-1212 Op ...

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Table 114. Op Code Map Abbreviations Abbreviation Description b Bit position cc Condition code X 8-bit signed index or displace- ment DA Destination address ER Extended Addressing Register IM Immediate data value Ir Indirect Working Register IR Indirect Register Irr ...

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Figures 29 and 30 provide information about each of the eZ8 CPU instructions 1.1 2.2 2.3 2.4 BRK SRP ADD ADD ADD 0 IM r1,r2 r1,Ir2 R2,R1 2.2 2.3 2.3 2.4 RLC RLC ADC ADC ADC ...

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