Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 171

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Z8F011ASH020EG2156

Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F011ASH020EG2156

Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V

Available stocks

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Price
Part Number:
Z8F011ASH020EG2156
Manufacturer:
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Quantity:
266
®
Z8 Encore!
F0830 Series
Product Specification
153
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watchdog Timer Oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The failure detection circuitry can be enabled anytime after a
successful write of OSCSEL in the Oscillator Control Register.
The Internal Precision Oscillator is enabled by default. If the user code changes to a differ-
ent oscillator, it may be appropriate to disable the IPO for power savings. Disabling the
IPO does not occur automatically.
Clock Failure Detection and Recovery
Primary Oscillator Failure
The Z8F04xA family devices can generate nonmaskable interrupt-like events when the
primary oscillator fails. To maintain system function in this situation, the clock failure
recovery circuitry automatically forces the Watchdog Timer Oscillator to drive the system
clock. The Watchdog Timer Oscillator must be enabled to allow the recovery. Although
this oscillator runs at a much slower speed than the original system clock, the CPU contin-
ues to operate, allowing execution of a clock failure vector and software routines that
either remedy the oscillator failure or issue a failure alert. This automatic switch-over is
not available if the Watchdog Timer is the primary oscillator. It is also unavailable if the
Watchdog Timer Oscillator is disabled, though it is not necessary to enable the Watchdog
Timer reset function outlined in the Watchdog Timer chapter of this document.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 KHz ±50%. If an external signal is selected as the system oscillator, it is
possible that a very slow but nonfailing clock can generate a failure condition. Under these
conditions, do not enable the clock failure circuitry (POFEN must be deasserted in the
OSCCTL Register).
Watchdog Timer Failure
In the event of failure of a Watchdog Timer Oscillator, a similar nonmaskable interrupt-
like event is issued. This event does not trigger an attendant clock switch-over, but alerts
the CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a
primary oscillator failure. The failure detection circuitry does not function if the Watchdog
Timer is used as the primary oscillator or if the Watchdog Timer Oscillator has been dis-
abled. For either of these cases, it is necessary to disable the detection circuitry by deas-
serting the WDFEN bit of the OSCCTL Register.
The Watchdog Timer Oscillator failure detection circuit counts system clocks while look-
ing for a Watchdog Timer clock. The logic counts 8004 system clock cycles before deter-
mining that a failure has occurred. The system clock rate determines the speed at which
the Watchdog Timer failure is detected. A very slow system clock results in very slow
detection times.
PS025113-1212
Operation

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