Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 167
Manufacturer Part Number
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Specifications of Z8F011ASH020EG2156
Data Bus Width
Maximum Clock Frequency
Program Memory Size
Data Ram Size
Package / Case
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
Number Of Timers
Program Memory Type
Supply Voltage - Max
Supply Voltage - Min
The device enters DEBUG Mode when this bit is 1. When in DEBUG Mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and breakpoints are enabled. If the
Flash read protect option bit is enabled, this bit can only be cleared by resetting the device. It
cannot be written to 0.
0 = The Z8 Encore! F0830 Series device is operating in NORMAL Mode.
1 = The Z8 Encore! F0830 Series device is in DEBUG Mode.
This bit controls the behavior of the BRK instruction (opcode 00H). By default, breakpoints
are disabled and the BRK instruction behaves similar to an NOP instruction. If this bit is 1
when a BRK instruction is decoded, the DBGMODE bit of the OCDCTL register is automati-
cally set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug acknowledge character (FFH) to the host when a breakpoint occurs.
0 = Debug acknowledge is disabled.
1 = Debug acknowledge is enabled.
These bits are reserved and must be programmed to 0000.
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This
bit is automatically cleared to 0 at the end of the reset sequence.
0 = No effect.
1 = Reset the Flash read protect option bit device.
Table 96. OCD Control Register (OCDCTL)
On-Chip Debugger Control Register Definitions