CY62148EV30LL-45ZSXI Cypress Semiconductor Corp, CY62148EV30LL-45ZSXI Datasheet - Page 6

• Manufacturer Part Number: CY62148EV30LL-45ZSXI
• Description: IC SRAM 4MBIT 45NS 32TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62148EV30LL-45ZSXI

• Memory Size: 4M (512K x 8)
• Package / Case: 32-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Organization: 512 K x 8
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3 V
• Memory Configuration: 512K X 8
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Density: 4Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Supply Current: 20mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2076; CY62148EV30LL-45ZSXI

Switching Characteristics
(Over the Operating Range)
Notes
Document #: 38-05576 Rev. *K
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
17. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
18. SOIC package is available only in 55 ns speed bin.
19. At any given temperature and voltage condition, t
20. t
21. The internal write time of the memory is defined by the overlap of WE, CE = V
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
pulse levels of 0 to V
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
HZOE
Parameter
, t
HZCE
[21]
, and t
HZWE
CC(typ)
transitions are measured when the output enter a high impedance state.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Up
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
, and output loading of the specified I
[17]
Description
[19]
[19]
HZCE
[19, 20]
[19, 20]
[19, 20]
[19]
is less than t
OL
/I
LZCE
OH
as shown in the
, t
HZOE
-45 (Industrial/Auto-A)
IL
Min
. All signals must be ACTIVE to initiate a write and any of these signals can terminate
45
10
10
45
35
35
35
25
10
is less than t
5
0
0
0
0
AC Test Loads and Waveforms on page 5.
LZOE
, and t
Max
45
45
22
18
18
45
18
HZWE
is less than t
Min
55
10
10
55
40
40
40
25
10
CY62148EV30 MoBL
5
0
0
0
0
LZWE
-55
for any given device.
[18]
Max
55
55
25
20
20
55
20
CC(typ)
Page 6 of 15
Unit
/2, input
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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