CY62148EV30LL-45ZSXI Cypress Semiconductor Corp, CY62148EV30LL-45ZSXI Datasheet - Page 8

• Manufacturer Part Number: CY62148EV30LL-45ZSXI
• Description: IC SRAM 4MBIT 45NS 32TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62148EV30LL-45ZSXI

• Memory Size: 4M (512K x 8)
• Package / Case: 32-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Organization: 512 K x 8
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3 V
• Memory Configuration: 512K X 8
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Density: 4Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Supply Current: 20mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2076; CY62148EV30LL-45ZSXI

Switching Waveforms
Truth Table
Document #: 38-05576 Rev. *K
Notes
28. Device is continuously selected. OE, CE = V
29. WE is HIGH for read cycles.
30. Address valid before or similar to CE transition LOW.
31. Data I/O is high impedance if OE = V
32. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
33. During this period, the I/Os are in output state. Do not apply input signals.
34. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
CE
ADDRESS
ADDRESS
DATA I/O
DATA I/O
H
L
L
L
[34]
WE
WE
CE
CE
WE
X
H
H
L
NOTE 33
OE
X
H
X
L
t
SA
High Z
Data Out
High Z
Data in
IH
(continued)
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)
.
t
HZWE
Figure 6. Write Cycle No. 2 (CE Controlled)
IL
Inputs/Outputs
.
t
SA
t
AW
t
AW
t
SCE
t
t
WC
WC
t
PWE
Deselect/Power down
Read
Output Disabled
Write
t
PWE
t
DATA VALID
DATA VALID
t
SCE
SD
t
SD
Mode
[31, 32]
[32]
t
HD
t
t
HA
LZWE
CY62148EV30 MoBL
t
HA
t
HD
Standby (I
Active (I
Active (I
Active (I
CC
CC
CC
Power
SB
)
)
)
)
Page 8 of 15
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