NAND16GW3F2AN6E NUMONYX, NAND16GW3F2AN6E Datasheet - Page 14

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NAND16GW3F2AN6E

Manufacturer Part Number
NAND16GW3F2AN6E
Description
IC FLASH 16GBIT SLC 48TSOP
Manufacturer
NUMONYX
Datasheet

Specifications of NAND16GW3F2AN6E

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
16G (2G x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Signal descriptions
3.7
3.8
3.9
3.10
14/65
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, V
program or erase operations.
It is recommended to keep the Write Protect pin Low, V
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can identify if the P/E/R controller
is currently active.
When Ready/Busy is Low, V
operation completes, Ready/Busy goes High, V
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low indicates that one, or more, of the memories is
busy.
During power-up and power-down a minimum recovery time of 10 µs is required before the
command interface is ready to accept a command. During this period the Ready/Busy signal
is Low, V
Refer to
calculate the value of the pull-up resistor.
V
V
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V
Table 19: DC
during power transitions.
Each device in a system should have V
widths should be sufficient to carry the required program and erase currents.
V
Ground, V
ground.
DD
DD
SS
provides the power supply to the internal core of the memory device. It is the main
ground
supply voltage
Section 12.1: Ready/Busy signal electrical characteristics
OL
SS,
.
characteristics) to protect the device from any involuntary program/erase
is the reference for the power supply. It must be connected to the system
OL
, a read, program or erase operation is in progress. When the
DD
decoupled with a 0.1 µF capacitor. The PCB track
OH
IL
.
, the device does not accept any
NAND08GW3F2A, NAND16GW3F2A
IL
, during power-up and power-down.
DD
is below V
for details on how to
LKO
(see

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