NAND16GW3F2AN6E NUMONYX, NAND16GW3F2AN6E Datasheet - Page 15

• Manufacturer Part Number: NAND16GW3F2AN6E
• Description: IC FLASH 16GBIT SLC 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND16GW3F2AN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 16G (2G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

NAND08GW3F2A, NAND16GW3F2A
4
4.1
4.2
4.3
4.4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section. See the summary in
Typically, glitches of less than 3 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
Command input
Command input bus operations give commands to the memory. Commands are accepted
when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low
and Read Enable is High. They are latched on the rising edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See
Address input
Address input bus operations input the memory addresses. Five bus cycles are required to
input the addresses (refer to
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See
Data input
Data input bus operations input the data to be programmed. Data is only accepted when
Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read
Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is
input sequentially using the Write Enable signal.
See
Data output
Data output bus operations read the data in the memory array, the status register, the
electronic signature, and the unique identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
If the Read Enable pulse frequency is lower then 33 MHz (t
output data is latched on the rising edge of Read Enable signal (see
data output after read AC
Figure 33
Figure 34
Figure 35
and
and
and
Table 20
Table 20
Table 20
waveforms).
for details of the timings requirements.
for details of the timings requirements.
for details of the timing requirements.
Table 5: Address
Table 4: Bus
insertion).
operations.
RLRL
higher than 30 ns), the
Figure 36: Sequential
Bus operations
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