NAND16GW3F2AN6E NUMONYX, NAND16GW3F2AN6E Datasheet - Page 29

• Manufacturer Part Number: NAND16GW3F2AN6E
• Description: IC FLASH 16GBIT SLC 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND16GW3F2AN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 16G (2G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

NAND08GW3F2A, NAND16GW3F2A
6.2.3
Multiplane page program
The devices support multiplane page program, that allows the programming of two pages in
parallel, one in each plane.
A multiplane page program operation requires two steps:
1.
2.
As for standard page program operations, the device supports random data input during
both data loading phases.
Once the multiplane page program operation has started, maintaining a delay of t
status register can be read using the Read Status Register command.
If the first or second page program fails, the fail bit of the status register is set: the device
supports a pass/fail status of each plane (I/O0: total; I/O1: plane0; I/O2: plane1).
The first step loads serially up to two pages of data (8448 bytes) into the data buffer. It
requires:
–
–
–
–
The second step programs, in parallel, the two pages of data loaded into the data buffer
into the appropriate memory pages. It is started by issuing a Program Confirm
command.
One clock cycle to set up the Page Program command (see
input)
Five bus write cycles to input the first page address and data. The address of the
first page must be within the first plane (A19 = 0)
One bus write cycle to issue the page program confirm code. After this the device
is busy for a time of t
When the device returns to the ready state (ready/busy high), a multiplane page
program setup code must be issued, followed by the second page address (5 write
cycles) and data. The address of the second page must be within the second
plane (A19=1), and A18 to A13 must be the address bits loaded during the first
address insertion
BLBH5
Section : Sequential
Device operations
BLBH5
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