ST72C334J2B6 STMicroelectronics, ST72C334J2B6 Datasheet - Page 31

• Manufacturer Part Number: ST72C334J2B6
• Description: 8-bit Microcontrollers - MCU Flash 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72C334J2B6

• Product Category: 8-bit Microcontrollers - MCU
• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.2 V to 5.5 V
• Package / Case: SDIP-42
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 8
• Data Rom Size: 256 B
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Program Memory Type: Flash
• Factory Pack Quantity: 13
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 3.2 V

9.4 CLOCK SECURITY SYSTEM (CSS)
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a clock filter control and an In-
ternal safe oscillator. The CSS can be enabled or
disabled by option byte.
9.4.1 Clock Filter Control
The clock filter is based on a clock frequency limi-
tation function.
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
If the oscillator is not working properly (e.g. work-
ing at a harmonic frequency of the resonator), the
current active oscillator clock can be totally fil-
tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped au-
tomatically and the oscillator supplies the ST7
clock.
9.4.2 Safe Oscillator Control
The safe oscillator of the CSS block is a low fre-
quency back-up clock source (see
If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe oscillator
period, the safe oscillator delivers a low frequency
clock signal which allows the ST7 to perform some
rescue operations.
Automatically, the ST7 clock source switches back
from the safe oscillator if the original clock source
recovers.
Figure 17. Clock Filter Function and Safe Oscillator Function
f
f
f
f
f
OSC
CPU
OSC
SFOSC
CPU
/2
/2
Figure
17).
Limitation detection
The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the CRSR register
description.
9.4.3 Low Power Modes
9.4.4 Interrupts
The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Note 1: This interrupt allows to exit from active-halt
mode if this mode is available in the MCU.
WAIT
HALT
CSS event detection
(safe oscillator acti-
vated as main clock)
Mode
Interrupt Event
ST72334J/N, ST72314J/N, ST72124J
No effect on CSS. CSS interrupt cause the
device to exit from Wait mode.
The CRSR register is frozen. The CSS (in-
cluding the safe oscillator) is disabled until
HALT mode is exited. The previous CSS
configuration resumes when the MCU is
woken up by an interrupt with “exit from
HALT mode” capability or from the counter
reset value when the MCU is woken up by a
RESET.
CSSD
Event
Flag
Description
Control
Enable
CSSIE
Bit
from
Wait
Exit
Yes
Halt
from
31/153
Exit
No
1)