CY7C1308DV25C-167BZC Cypress Semiconductor Corp, CY7C1308DV25C-167BZC Datasheet - Page 2

• Manufacturer Part Number: CY7C1308DV25C-167BZC
• Description: IC SRAM 9MBIT 167MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1308DV25C-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR
• Memory Size: 9M (256K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Selection Guide
Pin Configuration
Pin Definitions
Document #: 001-04310 Rev. *A
Maximum Operating Frequency
Maximum Operating Current
Shaded areas contain advance information.
DQ
LD
A, A0, A1
R/W
C
G
M
[35:0]
A
B
C
D
E
F
H
K
L
N
P
R
J
Name
TDO
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
GND/144M NC/36M
Parameter
Synchronous
Synchronous
Synchronous
Synchronous
DQ27
DQ29
DQ30
DQ31
DQ33
DQ35
Input/Output
V
TCK
Input Clock
NC
NC
NC
NC
NC
NC
REF
2
Input
Input
Input
I/O
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
V
DDQ
3
A
CY7C1308DV25C (256K × 36) – 11 × 15 FBGA
Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks
during valid Write operations. These pins drive out the requested data during a Read
operation. Valid data is driven out on the rising edge of both the C and C clocks during
Read operations or K and K when in single clock mode. When Read access is deselected,
Q
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and Read/Write direction. All transactions
operate on a burst of 4 data (two clock periods of bus activity).
Address Inputs. These address inputs are multiplexed for both Read and Write opera-
tions. A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. Eighteen address inputs are needed to access the entire memory
array. All the address inputs are ignored when the part is deselected.
Synchronous Read/Write Input. When LD is LOW, this input designates the access
type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must
meet the setup and hold times around edge of K.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See
[35:0]
V
V
V
V
V
V
V
R/W
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
4
A
SS
SS
SS
SS
are automatically tristated.
PRELIMINARY
V
V
V
V
V
NC
V
V
V
V
NC
5
A
A
A
A
DD
DD
DD
DD
DD
SS
SS
SS
SS
250 MHz
250
850
V
V
V
V
V
V
V
V
V
A0
6
K
K
A
C
C
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
NC
NC
Description
A1
7
A
A
A
DD
DD
DD
DD
DD
SS
SS
SS
SS
200 MHz
200
700
V
V
V
V
V
V
V
V
V
V
V
LD
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
Figure 1
8
SS
SS
SS
SS
NC/18M GND/72M
on page 5 for further details.
V
167 MHz
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DDQ
A
9
167
600
CY7C1308DV25C
DQ17
DQ15
DQ13
DQ12
DQ11
V
DQ9
TMS
NC
NC
NC
NC
NC
NC
10
REF
Unit
MHz
mA
DQ16
DQ14
DQ10
Page 2 of 18
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
TDI
CQ
ZQ
11
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