CY7C1308DV25C-167BZC Cypress Semiconductor Corp, CY7C1308DV25C-167BZC Datasheet - Page 8

• Manufacturer Part Number: CY7C1308DV25C-167BZC
• Description: IC SRAM 9MBIT 167MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1308DV25C-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR
• Memory Size: 9M (256K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
Document #: 001-04310 Rev. *A
t
Cycle Time
t
t
t
t
t
Setup Times
t
t
t
Hold Times
t
t
t
Output Times
t
t
t
t
t
t
t
t
t
Shaded areas contain advance information.
Parameter
Notes
Power
CYC
KH
KL
KHKH
KHCH
SA
SC
SD
HA
HC
HD
CO
DOH
CHZ
CLZ
CCQO
CQD
CQDOH
CQHZ
CQLZ
17. Tested initially and after any design or process change that may affect these parameters.
18. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
Cypress
levels of 0.25V to 1.25V, and output loading of the specified I
[19]
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
SA
SC
SD
HA
HC
HD
CHQV
CHQX
CHZ
CLZ
CHCQV
CQHQV
CQHQX
CHZ
CLZ
Parameter
V
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising
edge)
Address Setup to Clock (K and K) Rise
Control Setup to Clock (K and K) Rise (LD, R/W)
D
Address Hold after Clock (K and K) Rise
Control Signals Hold after Clock (K and K) Rise ( LD ,
R/W )
D
C/C Clock Rise (or K/K in single clock mode) to Data
Valid
Data Output Hold after Output C/C Clock Rise (Active
to Active)
Clock (C and C) Rise to High-Z (Active to High-Z)
Clock (C and C) Rise to Low-Z
C/C Clock Rise to Echo Clock Valid
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Clock (CQ and CQ) Rise to High-Z (Active to High-Z)
21]
Clock (CQ and CQ) Rise to Low-Z
CC
[35:0]
[35:0]
(typical) to the First Access Read or Write
Over the Operating Range
Setup to Clock (K and K) Rise
Hold after Clock (K and K) Rise
Description
PRELIMINARY
OL
/I
OH
and load capacitance shown in (a) of AC test loads.
[20, 21]
[18]
[20, 21]
[20, 21]
[20,
–0.30
–0.30
Min
4.0
1.6
1.6
1.8
0.0
0.7
0.7
0.7
0.7
0.7
0.7
0.8
0.8
0.8
10
250 MHz
Max
0.40
0.40
2.5
1.6
3.0
3.0
2.4
–
–
–
–0.35
–0.35
Min
5.0
2.0
2.0
2.2
0.0
0.7
0.7
0.7
0.7
0.7
0.7
0.8
0.8
0.8
10
200 MHz
CY7C1308DV25C
Max
2.75
0.40
0.40
1.8
3.0
3.0
2.6
–
–
–
DDQ
–0.40
–0.40
Min
6.0
2.4
2.4
2.8
0.0
0.7
0.7
0.7
0.7
0.7
0.7
0.8
0.8
0.8
10
167 MHz
= 1.5V, input pulse
Page 8 of 18
Max
0.40
0.40
3.2
2.0
3.0
3.0
3.2
Unit
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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